Using the ALTLVDS_RX DDR in = DDR out?

[Altera_Forum]

Hi, 

 Can anyone tell me that by using ALTLVDS_RX core provided by Altera, and if i use deserialization factor of 6; if the input in DDR format, the output of this block will be in DDR format too?? or, the output of this block will be 6 non-DDR format binary output??   Thanks!  Michael:)

[Altera_Forum]

What's DDR format? A serialization factor of 6 means a single bit input(on the port) and a 6-bit output. You have to determine the word alignment. Note that it does use the DDR registers in the I/O cell, but that is somewhat irrelevant, as there will be another stage of serialization to get it down to /6.

[Altera_Forum]

--- Quote Start ---  What's DDR format? A serialization factor of 6 means a single bit input(on the port) and a 6-bit output. You have to determine the word alignment. Note that it does use the DDR registers in the I/O cell, but that is somewhat irrelevant, as there will be another stage of serialization to get it down to /6.  --- Quote End ---    DDR=double data rate, meaning a valid data is on the rising and also the falling edge of the fast clock. I know LVDS uses DDR format, but i am not sure what is the output format of ALTLVDS_RX.  And I am not sure what are you trying to say.  Michael

[Altera_Forum]

The data will be 6 bits per rising edge of the outclock, so SDR. It's independent of the I/O standard, so even if you make the inputs LVDS, it will still be SDR format into the fabric.

[Altera_Forum]

Both ALTLVDS_TX/RX accept SDR data and output SDR data. End to end its SDR. Only when the serialization factor is 2 the DDR registers are used and SERDES is not used.

[Altera_Forum]

--- Quote Start ---  Only when the serialization factor is 2 the DDR registers are used and SERDES is not used.  --- Quote End ---   Not quite right. Software SERDES (Cyclone series) uses DDR registers for all deserialization factors, hardware SERDES (Stratix, Arria) doesn't use it at all.  The original question isn't still clear to me. Normally you would supply a frame (slow) clock rather than a bit (fast) clock to a SERDES block, the fast clock is generated internally. So the difference between SDR and DDR is just an internal detail of the SERDES, which you don't have to care for.

[Altera_Forum]

--- Quote Start ---  The data will be 6 bits per rising edge of the outclock, so SDR. It's independent of the I/O standard, so even if you make the inputs LVDS, it will still be SDR format into the fabric.  --- Quote End ---     I think you are right.. so basically the ALTLVDS_RX does the job of ALTDDIO and shift register and bit allignment?   Michael

[Altera_Forum]

--- Quote Start ---  Not quite right. Software SERDES (Cyclone series) uses DDR registers for all deserialization factors, hardware SERDES (Stratix, Arria) doesn't use it at all.  The original question isn't still clear to me. Normally you would supply a frame (slow) clock rather than a bit (fast) clock to a SERDES block, the fast clock is generated internally. So the difference between SDR and DDR is just an internal detail of the SERDES, which you don't have to care for.  --- Quote End ---     The original question was, if the input for ALTLVDS_RX is in DDR format, what is the output format ? is it in SDR or DDR?

[Altera_Forum]

--- Quote Start ---  Both ALTLVDS_TX/RX accept SDR data and output SDR data. End to end its SDR.   --- Quote End ---     Are you sure? :eek: