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Valued Contributor III
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VHDL code for PISO shift register using JK

pleasetell me the code for PISO shift register usink JK flip flop.. 

I have my exama nd i ahve made almost 20 programs, bt i m nt ble to do this one.. 

please help me with this.. 

thanks..:) :) :)
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Valued Contributor III
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FPGAs use D flips and a parallel to serial shift is straightforward: 

 

 

signal shift_reg : std_logic_vector(7 downto 0); 

 

...on the clk edge: 

if load = '1' then 

shift_reg <= data_in; -- data_in 8 bits 

else 

shift_reg <= '0'&shift_reg(7 downto 1); 

end if; 

 

data_out <= shift_reg(0); -- data_out one bit 

 

You will need to control the load signal to inject one byte until serilised out. 

 

if you want JK flip then instantiate JK then convert it to D by connecting each data_in bit to J & K with one inverter before k. You are now using structural vhdl to connect up flips just like schematic. No practical sense since the JK is actually made from D in FPGAs - I think.
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Valued Contributor III
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please give me the code using JK flip flop.. 

actually it has come in my exams lot of times.. 

please..
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Valued Contributor III
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Out of my head: 

 

Instantiate 8 jkff primitives(see quartus help), declare 8 bit signal j,k,Q then connect j,k,Q nodes then on a clked process: 

 

if load = '1' then  

J <= data_in; 

k <= not data_in; 

else 

J <= '0'&Q(7 downto 1); 

K <= '0'&not Q(7 downto 1); 

end if; 

 

data_out <= Q(0); 

 

you will need to double check my indices... 

 

edit: sorry you don't need clked process as clk will be connected direct to clk port of flips.
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Valued Contributor III
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can u pls elaborate it.. 

m nt able to understand.. 

and sorry but i think this is not correct.
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Valued Contributor III
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--- Quote Start ---  

can u pls elaborate it.. 

m nt able to understand.. 

and sorry but i think this is not correct. 

--- Quote End ---  

 

 

JK flip does not pass data (it is not like D flip), hence I convert it to D flip by inverting k input. if inputs are 01 then output is 0, if inputs are 10 then output is 1, hence it passes data and becomes like D flip.(the logic table may be the other way round, check that please). 

 

When load is high , input is passed to flips. when load is low(and should be low until data is serialised fully) then shift captured data through the pipe of flips with each j/k input pair driven by previous Q output. 

 

Hope this helps. There might be other ways of design please elaborate what could be wrong...
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Valued Contributor III
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ya i got this all.. 

but then why do we need to assign an input to K.. 

as we need J only to produce the output and to shift the bits.
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Valued Contributor III
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JK flip table says:  

j-----k-----Q 

0----1-----0 called reset 

1----0-----1 called set 

0----0-----0 

1----1---- inverts Q 

 

so the only way to pass data is using the reset/set cases.
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Valued Contributor III
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ya i know this table.. 

thnks.. 

i just try the program and will give u.. 

u pls give me ur comments over it.. 

thnx..
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Valued Contributor III
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Library IEEE; 

Use IEEE.STD_LOGIC_1164.ALL; 

Use IEEE.STD_LOGIC_ARITH.ALL; 

 

Entity piso is 

Port( D : in std_logic_vector(2 downto 0); 

CLK : in std_logic; 

Q : inout std_logic_vector(2 downto 0); 

QBAR : inout std_logic_vector(2 downto 0)); 

End piso; 

 

Architecture structural of piso is 

Component d_ff is 

Port (d,clk : in std_logic; 

q,qbar: inout std_logic); 

end t_ff; 

signal tmp:std_logic_vector:=”010”; 

Begin 

D<=temp; 

Wait for 10 ns; 

D2: d_ff portmap (d(2),’1’,q(2)qbar(2)); 

D1: d_ff portmap(d(1) ,’1’,q(1),qbar(1)); 

D0: d_ff portmap(d(0),’1’,q(0),qbar(0)); 

End structural; 

 

 

please tell me if its fine..
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Valued Contributor III
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Did you try to compile it? 

You have a signal that you define as 'tmp', but then use as 'temp'. 

You assign a value to the signal 'D', which is an input 

You use the 'wait' statement, that is only valid in a process 

You assign '1' to the clocks of your d_ffs, so they will never load any data 

This isn't a PISO, it's just 3 D flips in parallel. 

 

You'd better restart from scratch... 

First define your input/output ports. The ports you have here aren't right for a PISO. 

Then describe what the PISO should do 

Then see how J-K flips/flops are instantiated. 

Instantiate the flip/flops and write the process to control them.
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Valued Contributor III
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wadheraswati.... i tried the coding but it seems not working....

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Valued Contributor III
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Most HDL programmers would use a behavioral description for the shift register. if you're required to use a structural description with individual FFs, sketch a logic diagram on a piece of paper first. Besides the points already mentioned, you didn't connect a clock to the DFF. Not surprizing, the code does nothing.

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