Programmable Devices

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Programmable Devices

Discussions

unable to create symbol file for current file (Verilog HDL file) in Quartus IIweb13.1

Why only Soft PCS for Altera's XAUI IP in Arria 10 GX?

How to create filesystem for linux4 with nios2

PCie BAR to memory mapped slave

Issue Configuring MAX10: "Can't Access JTAG Chain"

Encounter error in building new webserver project in NiosII eclipse

memory initializing into 16-words per line instead of 4 words (initialize from ihex)

DDR3 HMC Timing issue with Qsys(device:5CGXFC5C6F27C7)

error of PCIE PERST_N whe running fitter!

DE0-Nano: Want to learn how to use

Cyclone V SoC - Shared Memory Controller

MAX10 Flash Memory specifications

Using SRAM on Altera DE2 in verilog

Adder Nightmare!

Configuration to PC

Featured Content

AGILEX5 - HPS-first - timeout waiting for RECONFIG_COMPLETED

SDI pinning on Agilex 5

10M04SCU324I7G - I/O timing

I350 igb driver failed with error -2

Request for the Product Lifecycle Status

Re: USB Blaster selection criteria

Solution: USB Blaster Driver for Windows 11 ARM

Re: MAX10 (Select Internal Configuration mode with ERAM )