VR Validation on ADL-S using IMVP9.1

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CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

VR Validation on ADL-S using IMVP9.1

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Hi Intel,

Thanks for your continued support on our projects. I am from Supermicro power lab and I'm currently working on a motherboard using a Gen5 VRTT and LGA1700 interposer. Our team is new to testing the ADL-S platform and we have some questions about the IMVP9.1 validation process.

Our current understanding is to use the IMVP9.1 Rev2.0 test plan to validate VCCCORE and VCCGT, along with the VCCIN_AUX Rev0.91 test plan for VCCIN_AUX, and the ROP Rev1.00 test plan for other power rails. Is this the correct approach for ADL-S?

I think once we confirm the test plans we will have more specific questions.

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