Hello.
I've been going through the "Cyclone V Schematic Review Worksheet" to check my design which incorporates a soft external memory interface (DDR2 - 64 bit data + 8*dm + differential dqs + 2*mem_clk connected to banks 5+6) and I have a question about valid pin locations for the mem_clk/mem_clk_n outputs.
The review worksheet states on page 81:
"mem_clk and mem_clk_n :
1)Place on any unused DQ or DQS pins with DIFFOUT capability for the mem_clk[n:0] and mem_clk_n[n:0] signals (where n>=0).
2)Do not place CK and CK# pins in the same
group as any other DQ or DQS pins.
3)If there are multiple CK and CK# pin pairs, place them on DIFFOUT in the same single DQ group of adequate width."
Banks 5+6 (5CGXBC7D6F31C7) together support 8 byte lanes and I am using all of them (64b interface) so where should I put the clocks? They must go within these two banks as they are the only 1V8 banks on the device.
Before reading this I successfully ran the EMIF core through Quartus with the clocks on V29/W29 and H27/G26 which would appear to break these rules.
Any help/clarification appreciated.
