Verify failed ---Leaving target processor paused

[Altera_Forum]

While programming flash with 1.2 Mb file I get error --- 

 Programmed 1074KB +78KB in 23.1s (49.8KB/s)  Verify failed at offset 60000 Verify failed at offset 80000 Verify failed at offset C0000 Leaving target processor paused  Can anyone help with a probable solution to this?

[Altera_Forum]

Could it be that these flash blocks are write protected and all others not ?

[Altera_Forum]

I checked, they are not write protected.

[Altera_Forum]

Did you check that your nios processor is connected correctly to your external memory in your top level module?  

When writing the nios processor does not know he is not writing in exisiting memory, but when reading/verifying no data is uploaded.

[Altera_Forum]

@ sanmao 

 i don't think that is the problem. he wrote    --- Quote Start ---  Verify failed at offset 60000 Verify failed at offset 80000 Verify failed at offset C0000   --- Quote End ---    and there is no verify failed at A0000 for me it looks at the first sight as if the external write protect is not set as some flash blocks are written, but some flash blocks can't be written to.  with cfi flash it is possible to lock individual flash blocks (regions) against overwriting and if the user want's to modify them, he needs to unlock these flash blocks. as fas as i know the nios 2 flash programmer does not check for locked flash blocks or even unlock them. i had one cfi flash that had locked blocks but the application never had the knowledge to lock them (reason was emc disturbance)  did you try to erase the complete flash ?  nios2-flash-programmer --erase-all ....   and check if the failed locations still hold the previous content.

[Altera_Forum]

now, i noticed that this verify failed error is coming at random addresses. After trying multiple times, once there was no error, and it programmed successfully. hence, i think there is some random behavior. 

 i am not getting what could be the cause of this randomness. maybe some loose connections? dont know. any idea regarding this

[Altera_Forum]

okay some question first, 

do you use the sopc builder with the cfi flash controller ? in that case did you check that the timing tab has the correct setup access and hold timing according to your cfi flash ?  is the write protect pin of the cfi flash pulled to a "enable" level or left floating ?  during programming of the cfi flash, could it be that anything else is accessing this device ? interrupt routine stored there ... the reason is during programming you must enshure that there is no access to this device that disturbs the programming sequence.

[Altera_Forum]

Have you instanciated a MMU in your CPU?

[Altera_Forum]

@mchmitt 

 actually, i have sram, ethernet, sdram, timer, and some PIOs in my hardware image, along with flash (attached to NIOS). I place that image inside FPGA (sof) before running flash programmer. I checked for timings, i found them to be correct. (this gives rise to one more doubt of mine, that if timings were wrong, then would memtest fail or pass? )

[Altera_Forum]

Actually, I asked for MMU because I couldn't access to my CFI through nios2-flash-programmer after having added a MMU to my cpu. 

I've found later that there is a option, '-M', to add for MMU support.