Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,632 Views

Verify failed between address <> and <> Leaving target processor paused

Folks, I have the following simple SRAM circuit built using Qsys.  

http://www.alteraforum.com/forum/attachment.php?attachmentid=13281&stc=1  

 

I then instantiated the circuit on a top level module and programmed the board.  

entity SRAM is port( CLK: in STD_LOGIC; led: out STD_LOGIC; --to/from SRAM fsm_dq: inout std_logic_vector(15 downto 0); fsm_addr: out std_logic_vector(19 downto 0); sram_lb_n: out STD_LOGIC; sram_ub_n: out STD_LOGIC; sram_ce_n: out STD_LOGIC; sram_oe_n: out STD_LOGIC; sram_we_n: out STD_LOGIC ); end SRAM; Architecture Arch of SRAM is component SRAM is port ( clk_clk : in std_logic := '0'; -- clk.clk reset_reset_n : in std_logic := '0'; -- reset.reset_n sram_DQ : inout std_logic_vector(15 downto 0) := (others => '0'); -- sram_0_external_interface.DQ sram_ADDR : out std_logic_vector(19 downto 0); -- .ADDR sram_LB_N : out std_logic; -- .LB_N sram_UB_N : out std_logic; -- .UB_N sram_CE_N : out std_logic; -- .CE_N sram_OE_N : out std_logic; -- .OE_N sram_WE_N : out std_logic -- .WE_N ); end component; begin SRAM_MAP: SRAM port map( clk_clk=>CLK, reset_reset_n=>'1', sram_DQ=>fsm_dq, sram_ADDR=>fsm_addr, sram_LB_N=>sram_lb_n, sram_UB_N=>sram_ub_n, sram_CE_N=>sram_ce_n, sram_OE_N=>sram_oe_n, sram_WE_N=>sram_we_n ); 

 

When I programmed Nios for a simple Read/Write memory test operations, I keep getting verify failed between address 0x204200 and 0x20FFFF(which is the memory address space of the SRAM) error. I set the on-chip memory size to the maximum possible. I don't know what is wrong. Any idea?  

 

Cheers,
0 Kudos
3 Replies
Altera_Forum
Honored Contributor I
361 Views

You should change your bsd to use the onchip memory as the main RAM (for .text, .data, .bss and .head). Then you can generate a memory test application that will test the SRAM from there. 

You can also add some Signaltap probes to the SRAM signals to check what the CPU is doing.
Altera_Forum
Honored Contributor I
361 Views

My onchip memory is the main RAM. I am using the Altera Monitor Program to program NIOS and here is the screen shot.  

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13290  

https://www.alteraforum.com/forum/attachment.php?attachmentid=13291
Altera_Forum
Honored Contributor I
361 Views

There must be something wrong then, because with those settings the Nios programmer shouldn't try to write to the addresses 0x204200 - 0x20FFFF. Are you sure you are using the correct bsp and that it has been recompiled?

Reply