Verilog Error I don't understand

[Altera_Forum]

I described this carry select adder ( 2 bits ); 

 module addercs(inu,ind,sum,cy); input [1:0] inu,ind; output [2:0] sum,cy; reg [2:0] sum; reg [2:0] cy;   always@(inu or ind)  begin:sumator  cy[0]=0;   sum[0]=inu[0]^ind[0]^cy[0];  cy[1]=(inu[0]&ind[0])|(cy[0]&(inu[0]^ind[0]));  sum[1]=(cy[1]&(inu[1]^ind[1]^1))|(~cy[1]&(inu[1]^ind[1]));  cy[2]=(cy[1]&((inu[1]&ind[1])|(1&(inu[1]^ind[1]))))|(~cy[1]&(inu[1]&ind[1]));  sum[2]=cy[2];  end endmodule    Here is the test banch for it:  module test_addercs ;  reg [1:0] ku,kd;  wire [2:0] su,c;   addercs# 4 Report(.inu(ku), .ind(kd), .su(sum), .c(cy));  initial begin   ku=0;kd=0;# 40 ;   $monitor("%d = ns" , $time ,,,"inu=%d ind=%d sum=%d cy=%d" ,ku,kd,su,c);    ku=2'b00;kd=2'b00;# 30 ;   ku=2'b00;kd=2'b01;# 30 ;   ku=2'b00;kd=2'b10;# 30 ;   ku=2'b00;kd=2'b11;# 30 ;   ku=2'b01;kd=2'b00;# 30 ;  ku=2'b01;kd=2'b10;# 30 ;  ku=2'b01;kd=2'b11;# 30 ;  ku=2'b10;kd=2'b10;# 30 ;  ku=2'b10;kd=2'b11;# 30 ;  ku=2'b11;kd=2'b11;     end endmodule   When i simulate i get this error and I don't understand why:  vsim work.test_addercs# vsim work.test_addercs # Loading work.test_addercs# Loading work.addercs# ** Error: (vsim-3006) I:/work/work/vlsida/fisiere sursa/cs/test_AdderCS.v(5): Too many inherited module instance parameters.# Region: /test_addercs# Error loading design   Any ideas? Thank you!

[Altera_Forum]

I think your problem is the "#4" in this line of code: 

 addercs# 4 Report(.inu(ku), .ind(kd), .su(sum), .c(cy));   When instantiating a module, the '#' is used to specify module parameters. But you haven't defined any parameters (only I/Os) So, simply remove the# 4 and I imagine it will compile.  Dan S.

[Altera_Forum]

Thank you Dan. But this dose not seem to be it.  

 Catalin T.

[Altera_Forum]

Do you mean that removing the# 4 from line 5 of the testbench did not resolve the problem?

[Altera_Forum]

yes. did not worked.

[Altera_Forum]

--- Quote Start ---  yes. did not worked.  --- Quote End ---    Hi,  removing the# 4 will solve the problem. Maybe you forgot to recompile the file ? You also have some naming problems between your model and the testbench.  module test_addercs ; reg [1:0] ku,kd; wire [2:0] su,c;  //addercs# 4 Report(.inu(ku), .ind(kd), .su(sum), .c(cy)); addercs report(.inu(ku), .ind(kd), .sum[/B](sum), .cy(cy));[/B]initial begin  ku=0;kd=0;# 40 ;  $monitor("%d = ns" , $time ,,,"inu=%d ind=%d sum=%d cy=%d" ,ku,kd,su,c);  ku=2'b00;kd=2'b00;# 30 ;  ku=2'b00;kd=2'b01;# 30 ;  ku=2'b00;kd=2'b10;# 30 ;  ku=2'b00;kd=2'b11;# 30 ;  ku=2'b01;kd=2'b00;# 30 ; ku=2'b01;kd=2'b10;# 30 ; ku=2'b01;kd=2'b11;# 30 ; ku=2'b10;kd=2'b10;# 30 ; ku=2'b10;kd=2'b11;# 30 ; ku=2'b11;kd=2'b11;   end endmodule   Kind regards  GPK

[Altera_Forum]

Regards to all. It works. Big thanks.