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WIRE buffer

Altera_Forum
Honored Contributor II
2,557 Views

Hi, 

 

So why exactly do we need to use a WIRE buffer? or any kind of buffer? 

to slow down the signal? 

 

Michael
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Altera_Forum
Honored Contributor II
1,232 Views

What's a wire buffer? You mean a "wire" primitive in Verilog?

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Altera_Forum
Honored Contributor II
1,232 Views

Yes, the "wire" primitive under the category buffer. 

Do you know what's the purpose of using WIRE? 

 

Michael:)
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Altera_Forum
Honored Contributor II
1,232 Views

The "wire" primive is meant to be a way to connect things. 

Put simply, a Verilog wire primite is really the same as a wire in a circuit schematic. 

 

Ie, if I instantiate a module, I need to use wires to connect it's outputs. 

I also need to use wires to handle tri-state. 

I can also use wires for combinational logic. 

 

There's no delay or whatever associated with a wire.
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Altera_Forum
Honored Contributor II
1,232 Views

rbugalho, 

 

Thanks! 

 

 

Mic
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