Warning: RST port on the PLL is not properly connected

[Altera_Forum]

Hello! 

I'm using PLL in my project for the Cyclone V device. And i have this warning in Quartus (Quartus Prime 16.0):    --- Quote Start ---  Warning: RST port on the PLL is not properly connected on instance pll100: pll100_inst|pll100_0002: pll100_inst|altera_pll:altera_pll_i|general[0].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock.  --- Quote End ---   In PLL IP Core (Name altera_pll, Version 16.0) settings i turn on PLL Auto Reset, but the warning did not disappear. So, it turns out that in any case i must manually control PLL reset port? Maby there is some guidelines how to do it? I have not found certain recommendations about it. Sorry for my english...

[Altera_Forum]

Hi coder, I recommend looking at Alex's suggestion in this thread, it helped me.  

http://www.alteraforum.com/forum/showthread.php?t=50680&p=208790#post208790  Basically drive the PLL reset based on the locked output. The recommendation to use a counter is a good idea.

[Altera_Forum]

--- Quote Start ---  Hi coder, I recommend looking at Alex's suggestion in this thread, it helped me.  http://www.alteraforum.com/forum/showthread.php?t=50680&p=208790#post208790  Basically drive the PLL reset based on the locked output. The recommendation to use a counter is a good idea.  --- Quote End ---   Thanks for the advice. The idea of Alex's suggestion is clear. It seems me strange that i turn on PLL Auto Reset (that automatically self-resets the PLL on loss of lock), PLL reconfiguration and clock switchover is not enabled in the design and i still have a warning: "The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock."

[Moki]

The thread with Alex's suggestion is no longer accessible with the old URL, but has been moved here:

https://forums.intel.com/s/question/0D50P00003yySnZSAU/reset-for-pll