Watchdog doesn't start

Altera_Forum · ‎04-03-2012

Hallo,

I try to use the WD component in my Qsys system. In general a very simple thing I thought.

- Add to system with a defined timeout period

- generate / build all

- start wd --> it runs and could never be stopped.

But here is the problem, it never starts. I found that:

http://www.altera.com/support/kdb/solutions/rd12152011_297.html?gsa_pos=1&wt.oss_r=1&wt.oss=watchdog

and I connected the chip select. Then I started re- compilation in quartus. But no effect.

Then I tried to see what the control register is set to.

    alt_printf("0x%x\n", IORD_ALTERA_AVALON_TIMER_CONTROL(WATCHDOG_BASE));
IOWR_ALTERA_AVALON_TIMER_CONTROL(WATCHDOG_BASE, 0x0004);
alt_printf("0x%x\n", IORD_ALTERA_AVALON_TIMER_CONTROL(WATCHDOG_BASE));

the output is always 0x00. It seems like the register write is not working.

I use Quartus 11.1 sp2. The project is for an C4. And I use the small_c_library and the reduced_device_driver option.

Could someone explain this behavior?

Any ideas?

Greets

Sim

Altera_Forum · ‎05-19-2012

I'm having the same issue. The problem seems to be that the top-level qsys verilog file (suggested in alteras watchdog fix) should not be edited and is overwritten by the system every compile... how can this be done?

Altera_Forum · ‎05-21-2012

Hallo,

I also tried several times to handle this bug... but the workaround didn't work for me. Like you say, the file is overwritten every time!

I decided to make my own watchdog component. It's very simple and works fine!

Greets