Community
cancel
Showing results for 
Search instead for 
Did you mean: 
KK000
Beginner
523 Views

What I/O standard shall I use in the pin planner to use a differential pair signal in a FPGA bank connected to 3.3V to compile my project ?

I am connecting VCCIO of some FPGA bank to 3.3 V for interfacing FPGA with ADC and DAC, Can anyone tell me what I/O standard should I give in .QSF for Differential inputs and outputs in Cyclone V FPGA.

0 Kudos
7 Replies
53 Views

Hello Kabilan, Can you kindly more elaborate on the ADC and DAC transmitter side ? It is also based on the IO frequency performance you would like to use. Also can I know which FPGA device you are using it ? Thank you , Regards, Sree
KK000
Beginner
53 Views

FPGA device I am using is CycloneV 5CSXFC6F31.

 

ADC and DAC used is AD9653 and AD9783 respectively.

Abe
Valued Contributor II
53 Views

For the ADC, the LVDS standard used is 1.8V LVDS, for this the FPGA interface should also match the same LVDS standrad and the IO Bank should be set as 1.8V LVDS.

For the DAC, the LVDS input range is from 800mV to 1600mV, so setting the FPGA interface for the DAC to 1.8V LVDS should work fine for this device too .

 

KK000
Beginner
53 Views

ok thanks.

 

Can I give "LVDS" as I/O standard for the fpga banks connected to 3.3 V power supply.

53 Views

Hello Kabilan , can you please refer the table 20 in below link , LVDS support the max VCCIO of 2.5V in cyclone V devices. https://www.intel.com/content/www/us/en/programmable/documentation/mcn1422497163812.html Thank you , Regards, Sree
KK000
Beginner
53 Views

Hi,

 

Actually what I want to know is If I am using I/O standard LVDS for DAC interfaced FPGA bank, does it supply 3.3V or 2.5V to DAC?

 

 

Thanks in Advance,

53 Views

sorry for very late response , It is depends on the what is your VCCIO bank supply where it is DAC channel is connected .

 

Thank you ,

 

Regards,

Sree

Reply