What files to version control of PLL IP entity?

[MTuck8]

I need to add a PLL entity to my otherwise very portable & clean VHDL code. When using the Quartus IP library wizard to create a PLL I end up with about 10-20 files​ in my projects some of which look copyrighted and some that do not seem suitable for version control (e.g. containing absolute paths or lots of machine generated meta data).

What files do I need to add to my open source project to be able to build the design - I'm hoping that it's a small subset of all those files.

Ideally the PLL entity should be portable between different Quartus versions and FPGA devices.​

More on this issue here: https://www.reddit.com/r/FPGA/comments/bzg9f9/version_control_of_intelquartus_megafunction/

[AndyN]

You just need the .ip file - everything else is generated from that during the IP Generation step in the Quartus flow.

[Rahul_S_Intel1]

Hi ,

I am requesting to use the mega wizard or IP catalog to generate the IP. And it is not at all recommended to copy paste the IP files between Qauartus versions.

[MTuck8]

So how can I share my design with other developers in tje open source community?

Should I request every developer to use the ​mega wizard to create a PLL entity that works with the design? Or perhaps creatr one set of IP files for every version of Quartus, and add them all to the Git repository?

[Rahul_S_Intel1]

Hi ,

You can Qar the project file and can share with other designers, the Qar file have all the settings and design file.. For making Qar from Quartus follow the below procedure.

Click Project in Quartus submenu Archive Project.

[MTuck8]

That does not sound like a good solution for an active open source project​ (you want all files to be in source form / plain text).

Is there no pure HDL solution for instantiating a PLL? For instance, block RAM and DSP functions (multiplication) can be infered from regular HDL constructs. An Intel library of common IP (e.g. a PLL) would be very useful.

[MTuck8]

So I found an HDL-only solution that worked for me, but it feels like a hack since the API seems to be undocumented.

It's based on the concept of instantiating an "​altera_pll" module in parameterized Verilog, and then wrap it in a VHDL component.

Source code here:​

https://github.com/mbitsnbites/fpga-ip/tree/master/pll

I have no idea how well it works between devices and Quartus versions.​

[kadon]

 perhaps creatr one set of IP files for every version of Quartus, and add them all to the Git repository?

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