What is the size of shared cache between CPU and FPGA in HARPv2?

[whan01]

I'm new to HARPv2 and interested in the shared cache structure. I just wonder what is the size of shared cache in HARPv2?

[MEIYAN_L_Intel]

Hi,

i had found that some information from the research paper as the document attached. In the document stated: "The FIU core not only contains the CCI-P, it also provides an IP cache in the FPGA, for the QPI channel, see Figure 1. This cache has a total capacity of 64 KiB, and is direct-mapped with 64 B cache lines. As the FPGA cache is included in the cache coherence domain of the CPU, the data in the FPGA cache is coherent with the CPU cache and the DDR memory" in Chapter 2.3.

Thanks

[whan01]

I have seen this paper before. I think 64KiB is the size of FPGA-private cache. What I try to find is the size of FPGA-CPU shared cache.

[MEIYAN_L_Intel]

Looking into the page 5 coherent cache system: https://raw.necst.it/2016/high-throughput-large-scale-sorting-on-a-cpu-fpga-heterogeneous-platform.pdf, is this the FPGA-CPU shared cache that you were looking for?

Thanks

[MEIYAN_L_Intel]

Hi,

According to https://www.microsigma.fr/media/seminaire/Intel-TCAI-Workshop-slides-Nov-2017/Day01-04-Accelerating_With_FPGA-Gaucheron.pdf shows the multiprocessor coherence domain for processor and FPGA. I hope this can help you out.

Thanks