Say a user design consists of an XOR gate.
Always @(*) C = A && ~B || ~A && B;
For whatever reason though the PCB does not connect input A to anything.
What is the default floating electrical state of input A? Is it guaranteed? Does leaving it floating incur ESD or device damage risk?
Depends on how the device was configured. Inputs have both a BUS HOLD and PASSIVE PULLUP option. Either one or the other, or neither, is possible. A CMOS input should not be left floating, it can just propagate noise otherwise. So the answer is 'it depends'.
If passive pullup is configured, then if unconnected it would be HIGH.
If bus hold is configured, then if unconnected it would be HIGH or LOW.
If neither of the above are configured (not recommended) it could be anything, possibly high frequency noise.
ak6dn et al,
I'm also concerned that stray low-current HV ESD impulse noise can fry an unconnected non-pulled up or non-bus-hold input, assuming it has negligible ESD withstand capability. Concern that a fairly low current ESD/surge stray can furthermore induce catastrophic latch-up .
What is even more concerning is what to do with a Cyclone IV's unconnected dedicated clock input pins! As far as I know there is no option for enabling bus hold or weak pullup in their assignments.
For any unused input, enable the passive pullup. No reasonable designer would let a CMOS input float. Don't do it.
Enable passive pullup, or add an external pullup/pulldown, as appropriate, for any iinput that may ever possibly not be driven by an external source.