What's the least expensive way to build a three-bit shift register?

[KSimo1]

I'd like to build a queue of three bits as inexpensively as possible. The queue has two input bits and one output bit. The inputs are <dataIn> and <shift>, and the output is <dataOut>. The bits are arranged from the left to the right, and can be implemented in any way imaginable, as long as it's as inexpensive as possible. In my mind's eye I'm thinking of something like a DRAM, where there's just one transistor/capacitor pair per each bit, but I don't know if that's possible.

The output <dataOut> always has the value of the bit on the right. While <shift> is low, all three bits just retain their current value. When <shift> goes high, the bit on the left takes the value of <dataIn>, the bit in the middle takes the former value of the bit on the left, and the bit on the right takes the former value of the bit in the middle.

In particular, I'm interested in whether or not this can occur with just three bits, or whether instead each bit has to have a master (set on one edge of changing <shift>) and a slave (set from the value of the master on the other edge).

Also, a size of three is just a fairly simple example of what I want to have; ultimately my design is going to need much larger groups of bits.

[KSimo1]

Wow, I really wasn't very clear in that article! I started out by mentioning a queue of three bits, and then went on to talk about three bits that consisted in two input bits and one output bit. I should have made it clear that the first group of three bits were not the same as the second group of three bits! Internal to the queue are three places each of which stores one bit. External to the queue are input bits <dataIn> and <shift>, and output bit <dataOut>. Output bit <dataOut> just takes the value of the rightmost internal bit. When <shift> is high, the leftmost internal bit takes the value of <dataIn>. And so on. Does that make more sense to everybody?

[sstrell]

It's still just a simple shift register (or FIFO). Are you looking to write it in RTL code? What exactly are you looking for?

#iwork4intel

[KSimo1]

Poster sstrell posted, "It's still just a simple shift register (or FIFO)."

Yes it is.

Then sstrell posted, "Are you looking to write it in RTL code? What exactly are you looking for?"

To be perfectly honest, I didn't know what RTL code meant. I did a Google search on it and got a web page that said something about VHDL code, so I implemented my bit queue in VHDL and created:

ENTITY bitQueue IS

 GENERIC( Exponent : INTEGER);

 PORT ( shift, dataIn : IN BIT;

     dataOut    : OUT BIT)

END bitQueue;

ARCHITECTURE bitQueue_bm OF bitQueue IS

 VARIABLE nmBits : INTEGER := 2 ** Exponent;

 SIGNAL contents : BIT_VECTOR( 1 TO nmBits);

BEGIN

 PROCESS

 BEGIN

  WAIT UNTIL shift'EVENT AND shift = 1;

  contents( 1) <= dataIn;

 END PROCESS;

 BITS : FOR bit IN 2 TO nmBits GENERATE

  PROCESS

  BEGIN

   WAIT UNTIL shift'EVENT AND shift = 1;

   contents( bit) <= contents( bit - 1);

  END PROCESS;

 END GENERATE;

 dataOut <= contents( nmBits);

END bitQueue_bm;

ARCHITECTURE bitQueue_ms OF bitQueue IS

 VARIABLE nmBits : INTEGER := 2 ** Exponent;

 SIGNAL masters : BIT_VECTOR( 1 TO nmBits);

 SIGNAL slaves  : BIT_VECTOR( 1 TO nmBits);

BEGIN

 PROCESS

 BEGIN

  WAIT UNTIL shift'EVENT AND shift = 1;

  masters( 1) <= dataIn;

  WAIT UNTIL shift'EVENT AND shift = 0;

  slaves( 1) <= masters( 1);

 END PROCESS;

 BITS : FOR bit IN 2 TO nmBits GENERATE

  PROCESS

  BEGIN

   WAIT UNTIL shift'EVENT AND shift = 1;

   masters( bit) <= slaves( bit - 1);

   WAIT UNTIL shift'EVENT AND shift = 0;

   slaves( bit) <= masters( bit);

  END PROCESS;

 END GENERATE;

 dataOut <= slaves( nmBits);

END bitQueue_ms;

I have both "bitQueue_bm" and "bitQueue_ms" because I don't know whether I want to have a master / slave situation or not.

I graduated from my university with a BS in Computer Science. Then later I went back and got my MS in Computer Science and Engineering. All I had to do to get my MS was come up with a design for a fairly useful hardware application. I never went beyond that rather high level design.

Now, I've started wondering what it would take to actually implement that design. What worries me is that the book I got on VHDL seems to indicate that with just the VHDL up above, I'm going to end up with a flip flop for each bit (maybe two flip flops per bit if I need to do master / slave), and as I understand it that will generate something on the order of eight transistors per flip flop.

On another thread someone asked me why I was worrying about the number of transistors I'm using. He said, "In an integrated circuit, they are virtually free." But I'm thinking of using each of these bits as the basic storage unit of my machine. Ultimately I'm thinking of having 3,758,096,128 bytes stored in my queues. At eight bits per byte and sixteen transistors per bit, that's 481,036,304,384 transistors. Are transistors really so virtually free that I can just toss 481 billion of them into my machine and not worry about the cost?

At any rate, what I'm trying to do is, as much as I can, cut down on the cost per bit of storage. DRAM does that pretty well, just having one transistor per bit of storage. Is there some way to implement a FIFO shift register, like the one I specified, without having much more than one transistor per bit?

Do I need to read up on RTL to do this? I'm willing to do pretty much whatever it takes to build my hardware application.

[EBERLAZARE_I_Intel]

Hi,

You could refer here on page on page 49 and 51 on shift registers and FIFO which could ease your understating;

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_memory.pdf

Regards.