This post has only a very indirect connection to FPGAs, but I don't know where else to post it, so I'm posting it here. If you can tell me where I can find a forum where the subject is more appropriate, that is just fine with me.
I'm trying to design a hardware sorting machine, with a number of processors proportional to the logarithm of the size of the data. The processors will be implemented as FPGAs, at least until I've got all the bugs worked out. The main data structures that the processors are going to work with will be shift registers. What I need at the most basic level is an array of z bits (where z is some power of two) and two input signals, a control bit and a data bit. If the control bit is low, then each bit in the array retains its previous value. If the control bit is high, then for each bit i where 0 < i < z, the bit at position i takes on the previous value of the bit at i-1, all in parallel in one clock cycle. The bit at position 0 takes on the single data input to the shift register. Whether the control bit is high or low, the output from the shift register is always the value of bit z-1.
Can I use an FPGA to implement this shift register too? Maybe I can, but I'm trying to look ahead to the way, way future day when I implement this shift register with as few transistors as possible. As I understand it, a DRAM lets you store data with one transistor and one capacitor per bit, which is a pretty impressive density. But due to the fact that when the control bit is high each bit in my shift register has to take on the value of the bit immediately adjacent to it, something it looks to me like a DRAM really can't do, I'm guessing I'm going to need to have more than one transistor plus one capacitor per bit. Can anyone tell me what the bare minimum of transistors would be that I would need per bit to build this shift register? A circuit diagram might be helpful too if you could include it.
I am not sure why you care about numbers of transistors? are you going to implement this in asic? also this could mean less, a FF might be directly from a standard lib so you do not have much control over there.
in verilog, it's simple to implement the shift register you described.....
LZhan65 posted, "I am not sure why you care about numbers of transistors?"
I want my sorting machine to be as inexpensive as possible, for potentially very large amounts of memory. For example, I'd like to be able to sort as many as 67,108,860 records, each record having up to 192 bits for the key and 64 bits for the rest of the record. If I were doing this with a DRAM, I'd only have one transistor-capacitor pair for each bit, but I think a DRAM architecture is fundamentally incompatible with the shift register that I need.
"are you going to implement this in asic?"
Eventually, once I get all the bugs worked out.
"in verilog, it's simple to implement the shift register you described....."
What are the pros and cons of using Verilog over VHDL for building something like the sorting machine I'm thinking of?
you should take a look at how a register is implemented using transistors, and also when designing asic, you use standard lib...
from what you described, you cannot design such big RAM on chip (cost and power!), so you should come up some clever algorithm or architecture (e.g. still using dram, but bigger on-chip ram as cache...)
If you are planning to use FPGA, to implement shift registers, you should not need to take care about the transistors. the logic algorithm will take care only you have to take care about the utilization of the FPGA.
In terms of VHDL or verilog in Intel FPGA, you should not need to take care a lot , the tool will use it on compiler