My design contains a DDR4(discrete component) EMIF, and I terminate the address/command/clk in the same way with Arria10 development kit DDR4 daughter card(DIMM). Here're my questions:
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Please refer to my answer below:
[Ans]: Terminate the DDR4 address, command, and control signals to VTT= 0.6V (VDD/2).
2. In daughter card, a resistor connects between CK0_T and CK0_C, but no resistor used to pull up CK0_T and CK0_C to VTT, should I add pull-up resistor for CK0_T and CK0_C?
[Ans]: No, no need to add resistor pull-up to VTT.
Hope this helps.
Thank you for your answer. But I still have some doubts.
CK0_T/CK0_C is differential clock output from FPGA to drive DDR4, not the reference clock input to FPGA.
According to the following figure in user guide, CK0_T/CK0_C should be pull-up to VTT.
So I would like to confirm the following conclusion with you: there's no need to add pull-up resistor for CK0_T/CK0_C, is that correct?
Thank you for the diagram and sorry for the confusion. My bad, I was not referring to FPGA output clock at first.
Yes, the CK0_T/CK0_C should be terminate pull-up to VTT. You need to follow the terminationguidline based on the I/O standard you used.