What's the suggested DDR3 memory layout for Cyclone V?

[Altera_Forum]

Hello, 

 Cyclone V hard- or software DDR3 controller don't support write leveling, so a "flyby" address and clock line topology can't be implemented due to too high delay skew. For the same reason, industry standard DDR3 DIMM modules can't be used with Cyclone V.  DDR3 memory designs are required to use discrete memory chips instead. The external memory interface handbook tells:     --- Quote Start ---  However, when you are designing the DDR3 SDRAM interface using discrete SDRAM components, you may desire a layout scheme that is different than the DIMM specification. You have the following two options:  Mimic the standard DDR3 SDRAM DIMM, using a fly-by topology for the memory clocks, address, and command signals. This options needs read and write leveling, so you must use the UniPHY IP with leveling.  Mimic a standard DDR2 SDRAM DIMM, using a balanced (symmetrical) tree-type topology for the memory clocks, address, and command signals. Using this topology results in unwanted stubs on the command, address, and clock, which degrades signal integrity and limits the performance of the DDR3 SDRAM interface.  --- Quote End ---    Obviously, only the second (bad) option is available for Cyclone V DDR3 designs. The interesting question is, if the memory speeds held out in prospect by the Cyclone V hardware manual and the external memory interface spec estimator (400 MHz with C6/C7, 333 MHz with C8) can be actually achieved? And how a reasonable PCB layout connecting recent 4Gb x8 chips in balanced tree topology to a Cyclone V hardware DDR3 interface looks like?   Best regards, Frank

[Altera_Forum]

I would also greatly appreciate some guidance from Altera on this issue.

[Altera_Forum]

Like you I searched a lot on the Altera website to find recommendations (...) for our DDR3 RAM Interface and did not find much. We are using an ArriaV that has no support for write leveling just as the CycloneV. The EMI Handbook has a few recommendations and at one point some numbers for max. skew etc. 

 The balanced tree topology (T shape) is not a bad topology at those frequencies. As DDR2 DIMMs have the same topology and also work up to (and somewhat above) 400MHz a layout for two components should not be that difficult or degrade performance. The critical signals are the command/ADR signals and of course the skew between them. If you stay in the specified ranges and use a proper termination scheme there shouldn't be any problems. If you are not sure about your signal integrity, you can perform simulations using tools like Hyperlinx. We did that with our ArriaV with two x16 components connected. Running the interface with 533 MHz shouldn't be a major problem so I think 400MHz should be possible for a CycloneV device. [We terminate the command lines directly at the star point and not behind every single component. Simulation results showed us that this is better for our setup. All signal lines are 50 ohms.]  I would suggest to use x16 components instead of the x8 ones to reduce the load on the command and address lines. When selecting the memory chips, be aware that there are dual-die components available that have of course a higher load than single-die types, especially when you are looking for 4Gb chips! As far as I know Micron has new 4Gb x16 single die components listed as samples on their website.  There is an ArriaV demoboard coming out quite soon. This includes a dual x32 DDR3 Interface. Look for arriaVGX_5agxfb3hf35es_start on the Altera FTP Server ( ftp://ftp.altera.com/outgoing/devkit/11.1/ ). On youtube I found a short but informing video, just search for DDR3 layout.