Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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When the signaltap enabled,the Fmax will be improved,why?

Altera_Forum
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I feel this is very strange,All my colleagues have experienced this phenomenon,Who can tell me why。 

Thank you!
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Altera_Forum
名誉コントリビューター II
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Timing tools see signaltap logic as any other mass of extra logic. If your fmax gets better it might well get better by even changing the fitter random seed for the same design(without making any change).  

If a device if full and streched it may show wild variation even by changin one statement ot timestamp value.
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