Why Arria 10 max & min delay difference on the same logic path is much larger than stratix IV?

[XYin01]

The difference on Arria 10 is around 1.5~3ns for the same logic, while that on stratix IV is around 0.3~0.5ns.

It is really hard for timing constraint.

Arria 10 is a high performance FPGA too. Why there is so much difference?

By the way, Stratix IV has D1 D2 D3 delay chain, the variation is small too, around 1ps. while Arria 10's output delay chain is around 3 ns.

It realy bad news for FPGA design engineer.

[KhaiChein_Y_Intel]

Hi,

We have four classes of FPGAs to meet your market needs, Intel Stratix, Intel Arria, Intel Cyclone and Intel Max, from the industry’s highest density and performance to the most cost effective. They have different architectures and you will see differences between all the device families.

For Arria 10 device, you can change the output delay chain settings

set_intance_assignment –to -name OUTPUT_DELAY_CHAIN <0..15>

Reference:https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf

Thanks.