Why Cyclone III cost as much power as Cyclone II?

[Altera_Forum]

I believe 65nm process technology can help to lower power consumption than 90nm. 

However the POWERPLAY and board test result did not agree with that. I have a design for data transceiving using RS485.The FPGA is in charge of 8B/10B,CRC,RS. Nios core is used. I change the project from CycloneII to Cyclone III,simulate the two project with powerplay using vcd files.The result showed the power comsumption are nearly the same. I have two PCB board with same design and different FPGAs,EP2C35 and EP3C40.The EP3C40 board comsumes a little more power than EP2c35 did. And the 2.5V power comsums 50-80mw,while EP2c35 do not have a 2.5v comsumption. This confuse me a lot . I use quartus 8.1. 50% logic.

[Altera_Forum]

Clearly, the analog voltage regulators for PLL analog supply generates additional losses. In addition, 65 nm technology must be expected to have higher static power consumption due to leakage currents. Did you compare the supply currents of 1V2 and 3V3 node for both designs in power play simulation and real design operation?