Why H2F AXI interface provide only 32 bit width but takes 128 bits?

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Why H2F AXI interface provide only 32 bit width but takes 128 bits?

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Hello!

I am using DE0-Nano-SoC and Atlas GHRD and GSRD

I created my own Avalon-MM component which has 64 bits output and one word span. It just assigns combinationaly 0xFEDCBA9876543210 to avalon_s0_readdata.

First question is why it takes 0xF bytes of address space in Qsys while requires only 8?

But what is realy annoying is that when I am reading this data in Linux I am getting only 0x76543210 and 3 more 32 bit words filled with zeros.

Changing HPS-2-FPGA data width in Qsys does not help. Currently it set to 128 bits.

Could anybody guess why I have this word reduction and how to fix it?

I was not regenerated bootloader after update in Qsys. Can it cause such problem?

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