Why does fitting fail when there are still resources available?

[student8]

Layout and routing resources are still available, but layout fails.

The Quartus error is as follows:

Error (170143): Final fitting attempt was unsuccessful
Info (170138): Failed to route the following 2 signal(s)
Info (170139): Signal "tic:tic0|Add3~1"
Info (170139): Signal "tic:tic0|WideOr2~2"
Info (170140): Cannot fit design in device -- following 2 routing resource(s) needed by more than one signal during the last fitting attempt
Info (170141): Routing resource LAB Input (X48_Y30, I17)
Info (170141): Routing resource LAB Input (X48_Y30, I48)

Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

What are the possible reasons for fitting failure?

[FvM]

Hi,
fitting failure with a rather low resource utilisation indicates that your design sets special constraints that can't be fulfilled by Quartus. Can be e.g. incompatible  location assignments or WYSIWYG primitives. 

Unlikely to happen in regular design.

[student8]

Thank you for your response. I am debugging an FPGA chip embedded in a fixed development board, and I cannot arbitrarily change pin assignments; the input and output pins are fixed. I would like to ask how to modify the code or change software settings to make the fitter pass in this situation. For example, how should I resolve the following error?

Info (170138): Failed to route the following 2 signal(s)
Info (170139): Signal "tic:tic0|Add3~1"
Info (170139): Signal "tic:tic0|WideOr2~2"

Info (170140): Cannot fit design in device -- following 2 routing resource(s) needed by more than one signal during the last fitting attempt
Info (170141): Routing resource LAB Input (X48_Y30, I17)
Info (170141): Routing resource LAB Input (X48_Y30, I48)

[SyafieqS]

You probably need to check some assignment location set up that is illegal to fitter. That might be the reason and change it accordingly

[student8]

Thank you for your response. I am debugging an FPGA chip embedded in a fixed development board, and I cannot arbitrarily change pin assignments; the input and output pins are fixed. I would like to ask how to modify the code or change software settings to make the fitter pass in this situation. For example, how should I resolve the following error?

Info (170138): Failed to route the following 2 signal(s)
Info (170139): Signal "tic:tic0|Add3~1"
Info (170139): Signal "tic:tic0|WideOr2~2"

Info (170140): Cannot fit design in device -- following 2 routing resource(s) needed by more than one signal during the last fitting attempt
Info (170141): Routing resource LAB Input (X48_Y30, I17)
Info (170141): Routing resource LAB Input (X48_Y30, I48)

[sstrell]

You'd have to show some code.  Something is making the fitter think the two signals need to use the exact same resource, which is very odd.  Show code and any unique assignments you may have in the Assignment Editor or Pin Planner.

[SyafieqS]

Let me know if there is any update

[SyafieqS]

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