Why is the use of different PLL feedback modes in Altera devices?

[Altera_Forum]

The documentation states that the Altera PLLs have 6 different clock feedback modes. These are:  

 1. Direct mode 2. Normal mode 3. Source-Synchronous mode 4. External Feedback mode 5. Zero-Delay Buffer mode 6. LVDS mode   Why are there so many clock feedback modes and how do I know which one I need?

[Altera_Forum]

--- Quote Start ---  The documentation states that the Altera PLLs have 6 different clock feedback modes. These are:   1. Direct mode 2. Normal mode 3. Source-Synchronous mode 4. External Feedback mode 5. Zero-Delay Buffer mode 6. LVDS mode   Why are there so many clock feedback modes and how do I know which one I need?  --- Quote End ---    They are offered to tackle timing problems in case you have io violations. Direct : only de-jitters clock, does not compensate for delay. normal, de-jitters and reduces clock delay from pin to register and compensates for clock delay from pin source synchronous, keeps data/clk phase same between pins and registers external: relevant if so zero delay: relevant to an output clock from pll, maintains same phase of output clock as that of input clock. lvds: relevant to serdes.

[Altera_Forum]

if I am connecting a audio DAC that needs MCLK (master clock) and takes I2S signals SCLK, Data and LRCK (same frequency as audio sample rate, used to select left/right channels), and I intend to generate MCLK and other clock signals from a PLL inside the FPGA, which of these shall I need to use?