Xcievers communication between Cyclon10gx to Agillex F Tile FGT PMA direct

[Avichay]

Hello,

In our application we are designing  a Xcievers link between cyclon10GX device (10CX150YF672E6G)   to a intel Agillex F-TILE  (AGFB027R24C2E2VR0 )

On the Cyclone side we use PCS where  in the alignment section we use " automatic synchronization state machine "  . also the bit slip is disabled.

on the Agilex just use the direct PMA FGT .

Design Rate is 2Gbps.

I have concern regarding the alignment issue between the 2 FPGA's.

The PCS option tab (seen on the cyclon10gx)  is not seen on the Agillx FGT settings , so 

Is there any known  issue that prevents this communication alignments  ?

Can you guide for the right settings for it to work on both sides ? 

We understand the 8b/10b encoding need to be added by soft code on the Agillex side.

Thanks,

Avichay  

[Kshitij_Intel]

Hi Avichay,

Sorry for the late reply, For this issue of alignment, you need to implement the soft word-aligner. Sharing an article FYR.

https://www.intel.com/content/www/us/en/support/programmable/articles/000091250.html?erpm_id=2902066_ts1674570639286

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi Avichay,

Any update on this.

Thank you

Kshitij Goel

[Kshitij_Intel]

Hi Avichay,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you

Kshitij Goel

[Avichay]

sorry for the delay, just now updated the  intel community approval . thanks for the answer