a simple code showing a latch in quartus II?

Altera_Forum · ‎02-02-2012

Hi i am working in system verilog and a simple code like

always_ff @ (posedge clk , negedge rst_n)

begin

if (rst_n==1'b1)

begin

x<=a;

elseif (i==1'b1)

begin

x<=x+1'b1;

end

i am not using the exact name but the code is exactly the same where i is an input pin to the module.

its showing 2 warnings

Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

and

Warning (335093): Timing Analysis is analyzing one or more combinational loops as latches

for x these warning are coming.

Thanks

Altera_Forum · ‎02-02-2012

You can expect this warning for all recent FPGA families that don't have both asynchronous set and reset provided with their registers. They need to implement a rather complex circuit with a XORed data path on both sides of the register and a latch holding the asynchronous preset value. Besides the reported restrictions, the construct involves additional delay.

The preferred solution is to avoid an asynchronous variable preset.

Altera_Forum · ‎02-03-2012

Yes i was facing an additional delay when i checked the timing reports.

Thanks for the reason...