How can i make bidirectional pins virtual? :(

[Altera_Forum]

I am working on a design with bidirectional interfaces having an io count of more than 2000. I want to fit the design on a device and check its timings. But the max available pin count is hardly 1000. 

I cant use the virtual pin assignment as it is ignored for bidirectional pins. Is there anyother way to fit the design ?   Thanks

[Altera_Forum]

why do you have more than 2000 bidirections IOs? how do you expect these to work on a real chip? Bidirs internally are converted to muxes. Bidirectional signals should really only be connected to a pin. 

 If they were coded as separate ins and outs (as they will end up as eventually anyway) then you could easily use virtual pins.

[Altera_Forum]

Yes i know...but i am doing a module level synthesis. This module has some huge combo logic and i want to be aware of the timing so that i dont have probs at the top. 

Now coming back to interfaces , these wont be in the port list in the top, so i just want to do a module level synthesis as i doubt that this module might cause timing probs when i integrate it. So can you help me as to what i can do regarding this? Thanks :)

[Altera_Forum]

do you know SignalTapII? 

 you can watch signals inside of FPGA via JTAG  this document http://www.akiron.com/fpga/ (choose BaseProjectInVerilog) may help you to signaltapII

[Altera_Forum]

okk akira..i think this might help...thanks a lot..

[Altera_Forum]

try using an empty partition

[Altera_Forum]

hi pancake can you tell me more about empty partition...THANKS

[Altera_Forum]

now that i think about it, this still may not work. anyhow... 

 1. port map the bidir bus to an HDL file that defines the bidir I/O but nothing else 2. run Analysis and Elaboration 3. find the bidir dummy module in the Hiearchy window 4. right click and create a new parition 5. in Assignments > Design Partitions change the Netlist Type for the dummy partition to Empty

[Altera_Forum]

Ok thanks pancake...i will let you know the results.. :)

[Altera_Forum]

you could also create a dummy file that sepatates the bidir busses into separate in and out, and then make all the pins virtual.

[Altera_Forum]

Yes you mean to say a wrapper...i am doing that only ...thanks tricky...