dmx-512 vhdl/verilog code

[Altera_Forum]

can any one plz help me for my project. titled dmx-512 protocol used to control led brightness in video display systems..

[Altera_Forum]

Sure, what help do you need? (other than a finish project to copy/paste)

[Altera_Forum]

I need vhdl/verilog code for 100 channels usage with 100 different data sending through interface for controlling the brightness of LEDS.

[Altera_Forum]

There seems to be a dmx core at opencores (http://www.opencores.org). It is marked as beta, but it could be a good start. 

Did you have a look at the dmx specification? How will you control what to send on what channel?

[Altera_Forum]

ya i knw all the specs of DMX-512. 

In dmx-512 i want to use only 100 channels and i want to send some intensity values through channels to the pwm and that to LED tiles so that it controls the brightness of LED.  So 100 different values on 100 channels one data for 1 channel this is the procedure. DATA is 8-bit , 1 start and 2 stop bits along with BREAK, Mark before break and Mark after the break.  These are things which are to be included in the coding

[Altera_Forum]

I don't think you'll find a ready made code for that, except maybe in the opencore project (I didn't have a look at the files). 

But it doesn't sound too hard, so you can start coding it and if you have any specific question then we can answer them.

[Altera_Forum]

TO_BE_DONE

[Altera_Forum]

this is for receiver unit of DMX-512 which used anly 6 channels and same data 

------------------------------------------------------------------------------- -- Entity for Receive Unit - 250K DMX baudrate -- ------------------------------------------------------------------------------- library ieee;  use ieee.std_logic_1164.all;  use ieee.numeric_std.all; --library work; -- use work.UART_Def.all; ------------------------------------------------------------------------------- -- Receive unit ------------------------------------------------------------------------------- entity RxUnit is  port (  Clk : in Std_Logic; -- system clock signal  Reset : in Std_Logic; -- Reset input  RxD : in Std_Logic; -- RS-232 data input  BREAK : out Std_Logic; -- Status signal  DataIn : out Std_Logic_Vector(7 downto 0);  BitStart: out Std_Logic); end entity; --================== End of entity ==============================-- ------------------------------------------------------------------------------- -- Architecture for receive Unit ------------------------------------------------------------------------------- architecture Behaviour of RxUnit is  -----------------------------------------------------------------------------  -- Signals  -----------------------------------------------------------------------------  signal Start : Std_Logic; -- Syncro signal  signal tmpRxD : Std_Logic; -- RxD buffer  signal BreakDetected : Std_Logic; --   signal BitCnt : Unsigned(3 downto 0); --   signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter  signal ShtReg : Std_Logic_Vector(7 downto 0); --  signal DOut : Std_Logic_Vector(7 downto 0); -- begin  ---------------------------------------------------------------------  -- Receiver process  ---------------------------------------------------------------------  RcvProc : process(Clk,Reset,RxD)  variable tmpBitCnt : Integer range 0 to 15;  variable tmpSampleCnt : Integer range 0 to 15;  constant CntOne : Unsigned(3 downto 0):="0001";  begin  if Rising_Edge(Clk) then  --tmpBitCnt := ToInteger(BitCnt);  tmpBitCnt := To_Integer(BitCnt);  --tmpSampleCnt := ToInteger(SampleCnt);  tmpSampleCnt := To_Integer(SampleCnt);  if Reset = '0' then  BitCnt <= "0000";  SampleCnt <= "0000";  Start <= '0';  BreakDetected <= '0';  ShtReg <= "00000000"; --  DOut <= "00000000"; --  else  if Start = '0' then  if RxD = '0' then -- Start bit,   SampleCnt <= SampleCnt + CntOne;  Start <= '1';  BreakDetected <= '0'; -- clear output  end if;  else  if tmpSampleCnt = 8 then -- reads the RxD line  tmpRxD <= RxD;  --BitStart <= '1'; -- position marker for debugging  SampleCnt <= SampleCnt + CntOne;   elsif tmpSampleCnt = 15 then   --BitStart <= '0'; -- position marker for debugging case tmpBitCnt is  when 0 => -- Waiting for start bit (should be '0')  if tmpRxD = '1' then -- Not detected.  Start <= '0';  --tmpDRdy <= '0';  else  BitCnt <= BitCnt + CntOne;  end if;  SampleCnt <= SampleCnt + CntOne;  when 1|2|3|4|5|6|7|8 =>  BitCnt <= BitCnt + CntOne;  SampleCnt <= SampleCnt + CntOne;  ShtReg <= tmpRxD & ShtReg(7 downto 1);  when 9 => --1st stop bit  if tmpRxD = '0' then -- Check for stop bit (should be '1')  -- Stop bit not detected. Either fault, or BREAK signal.  BreakDetected <= '1';  BitCnt <= BitCnt + CntOne; -- Goto state 10 and wait for stop  SampleCnt <= SampleCnt + CntOne;  else  -- Stop bit found so reset and wait for  -- next falling edge of start bit.  BreakDetected <= '0';  BitCnt <= "0000"; -- Goto state 00 and wait for start  SampleCnt <= "0000";  Start <= '0';  end if;   DOut <= ShtReg;  when 10 =>   -- Ensure RxD is high before continuing...  -- This caters for BREAK byte length (88uS with no stop bits)  if BreakDetected = '1' then -- we are waiting for a return to a high state  if tmpRxD = '1' then -- check for high state  -- High state detected, so abandon this and wait for the falling  -- edge of the next START bit.  BitCnt <= "0000";   SampleCnt <= "0000";  Start <= '0';  end if;  SampleCnt <= SampleCnt + CntOne;  end if;    when others =>  null;  end case;    else  SampleCnt <= SampleCnt + CntOne;   end if;  end if;  end if; -- if reset=...  end if; -- rising clock  end process;   DataIn <= DOut;  BREAK <= BreakDetected;  BitStart <= Start; end Behaviour; --==================== End of architecture ===================  TX and th RX unit should combined den only v can run the code

[Altera_Forum]

The code that you have hardcodes the 6 channels as ports and it will be difficult to adjust it for 100. You'll probably need to change it so that it outputs on two ports the data and the channel number, instead of using one data output port per channel.

[Altera_Forum]

i have written the code for 100 channels also but iam getting some warnings like below., 

 Warning: No exact pin location assignment(s) for 813 pins of 813 total pins   Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details  Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.  Warning: Found 802 output pins without output pin load capacitance assignment  Warning: Can't generate programming files because you are currently using the Quartus II software in Evaluation Mode  Warning: Found pins functioning as undefined clocks and/or memory enables  Info: Assuming node "SysClk" is an undefined clock  Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew  Info: Detected ripple clock "RxUnit:RxDev|Start" as buffer  Warning: Circuit may not operate. Detected 38 non-operational path(s) clocked by clock "SysClk" with clock skew larger than data delay. See Compilation Report for details.

[Altera_Forum]

800 I/O pins is a lot. I assume you created 100 output ports with 8-bit vectors? As I said I think it would be more practical to have two ports instead, one with the channel number and another one with the value. 

The pin assingnment warning means exactly what it says. You forgot to assign pin numbers to your signals. You can do that on the pin planner, but I doubt you'll be able to fit all of them on your FPGA. For the evaluation mode warning, you either need to install a license or use the web edition of Quartus For the last 3 warnings it's probably a problem in your code.

[Altera_Forum]

Ya as DMX-512 data must be 8-bit data so per channel 8-bit data should be send. So how can I come out from this problem plzzzz say me because almost code has been done only these warnings are rising. Can you say what problem will be there in the code and how to overcome all the warnings. plzzzzzzzz

[Altera_Forum]

As I dsaid I think yo uneed to change your code to output a value and address instead of using 100 vectors for your outputs. It should start solving some of your problems.