Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
18512 Discussions

about MAX V ALTUFM Parallel Interface Timing Spec

Altera_Forum
Honored Contributor I
808 Views

Hi, 

 

From Altera mv51007.pdf document Table7-16 Parallel Inerface Timing follows the command cycle ( READ/WRITE/ERASE) command cycle varies from 600 ns to 3000 ns. What's the max. requested command time for the READ operation only? 

 

BR
0 Kudos
0 Replies
Reply