altera tse mac signal ff_tx_rdy

[Altera_Forum]

Hi  

  I am using tse mac ip for ethernet and i am getting rx side of sop & eop properly but i am getting the ff_tx_rdy low.  when rx side of sop is always low & eop is properly getting in this case ff_tx_rdy is getting high.  when ff_tx_rdy will get high and what is its functionality.

[Altera_Forum]

It looks like the transmit FIFO gets full and can't accept more data, that's why the ready signal becomes low. Now I don't know why the FIFO gets full and doesn't empty itself. Could you have a look at the signals between the MAC and the PHY? Is it trying to send anything? What kind of Ethernet link are you using? Is it full duplex?

[Altera_Forum]

--- Quote Start ---  It looks like the transmit FIFO gets full and can't accept more data, that's why the ready signal becomes low. Now I don't know why the FIFO gets full and doesn't empty itself. Could you have a look at the signals between the MAC and the PHY? Is it trying to send anything? What kind of Ethernet link are you using? Is it full duplex?  --- Quote End ---    Thanks. the full flag is indeed high. We are using full duplex. PHY is Marvel 88E1111 gigabit. TSE MAc is instantiated in SGMII triple speed mode.   This problem goes away when I loop the MAC ff_rx signals to the ff_tx signals and keep the ff_rx_rdy to high.   It also goes away when I connect the tx signals to a packet generator within the same FPGA.   When I open up the tx data signals, and take them to the FPGA pins, the tx ready goes low and fifo full flag goes high.   Question: At reset, is there any recommended levels at which the tx input lines including the clk to be held at? Should I control the tx_clk and rx_clk in any way? currently it is connected to a free running 50 MHz.

[Altera_Forum]

The tx_clk and rx_clk can be connected to any type of clock, just ensure that the tx and rx signals you are connecting to the TSE are synchronized with those clocks. 

Is the MAC receiving also the correct clocks on the PHY side? How is your ff_rx_rdy signal when you connect the tx signals to FPGA pins?

[Altera_Forum]

--- Quote Start ---  The tx_clk and rx_clk can be connected to any type of clock, just ensure that the tx and rx signals you are connecting to the TSE are synchronized with those clocks. Is the MAC receiving also the correct clocks on the PHY side? How is your ff_rx_rdy signal when you connect the tx signals to FPGA pins?  --- Quote End ---     Thanks Daixiwen.    The ff_rx_rdy signal is good - high - throughout and the ff_rx_data keeps receiving the data properly from the ethernet side. It is only the TX.   Now, I did one experiment. I took the working - loop backed tx and rx - project and change the tx_almost_full value to 3. The ff_tx_rdy again became permanently low.   I realise I do not understand the fifo thresholds properly. I intend to and am using the MAC in CUT THROUGH mode.   I have set up the fifo depth to 2K. I am using a 484 pin Cyclone iV 75 GX part.   What is the recommended values I should use to program the fifo thresholds? There seem to be four variable - the almost full, section_full, almost_empty and section_empty. For cut through mode I have set the section_full to the value 16 ( although I dont understand why, I have just done what the data sheet says).  Only when the other three seem to be at the hardware reset value (0) the loop back project seems to work. If I change these values it does not work. Once we set the cut through mode what is the relevance of the other variables?

[Altera_Forum]

I've never really paied attention to those, just using what Altera put in their driver IOWR_ALTERA_TSEMAC_RX_ALMOST_EMPTY(tse.mi.base, 8); IOWR_ALTERA_TSEMAC_RX_ALMOST_FULL(tse.mi.base, 8); IOWR_ALTERA_TSEMAC_TX_ALMOST_EMPTY(tse.mi.base, 8); IOWR_ALTERA_TSEMAC_TX_ALMOST_FULL(tse.mi.base, 3); IOWR_ALTERA_TSEMAC_TX_SECTION_EMPTY(tse.mi.base, tse_hw->tse_tx_depth - 16); //1024/4; IOWR_ALTERA_TSEMAC_TX_SECTION_FULL(tse.mi.base, 0); //32/4; // start transmit when there are 48 bytes IOWR_ALTERA_TSEMAC_RX_SECTION_EMPTY(tse.mi.base, tse_hw->tse_rx_depth - 16); //4000/4); IOWR_ALTERA_TSEMAC_RX_SECTION_FULL(tse.mi.base, 0); 

It seems that you are using the correct value. I don't really understand how they influence the core's functionality, but the multiple comments on tx_section_full seems to show that Altera isn't sure either ;) It may be a stupid question but are you sure that the tx path is enabled? You can check it by reading Command_config Register. Do you reset the TSE after changing the fifo registers? Altera recommends a reset after a speed change, but it could be useful too when changing the fifo registers.