altpll component query

[Altera_Forum]

I am using a DE2-115 board with Cyclone IVE. When I design something in SOPC, I just use one external clock input of 50 MHz, and then I use the altpll component in Quartus MegaWizard Plugin Manager to create clocks of higher frequency for the NIOS system and the sdram for example. For example, in the ALTPLL wizard I have as input 50 MHz, and two ouputs with multiplication factor 2 to give two 100 MHz output clocks. I then instantiate this module in my main .v file. So far so good. But when I open the generated pll module file and look at the 'defparam' section, it says: 

  altpll_component.inclk0_input_frequency = 20000, Where did that '20000' value come from? Is this value in Hz and does this mean my system and sdram are running at 40 kHz only? How do I increase this frequency?  Thank you.

[Altera_Forum]

I've just open a pll.v file ,and I see the same words : 

  --- Quote Start ---  altpll_component.inclk0_input_frequency = 20000,  --- Quote End ---   (my pll's input clk is 50M too)   I change the input clk freq to 100M ,the words changes to :   --- Quote Start ---  altpll_component.inclk0_input_frequency = 10000,  --- Quote End ---    So I think the number means the period of the input clk, the unit is psec.

[Altera_Forum]

Thanks MechanicalBoy. Stupid me for not finding that out! Can somebody also please tell me the maximum system clock frequency that I can send to the NIOS and sdram?

[Altera_Forum]

If you want to know the maximum system clock frequency your device can work normally. it mainly depends on the device (include fpga and sdram) and the temperature. 

You can use eda gate level simulation to see whether your design can work well on your input clock, which provided several models.  If you want to know the highest frequency pll can export, I don't know either, but I think it must be higher than your device's maximum input clock.

[Altera_Forum]

Thanks. I don't understand all what you wrote but I will try to make sense of it all soon. But my clock related questions are not over. In NIOS, system.h lists ALT_CPU_FREQ 50000000. The command alt_timestamp_freq() also returns 50 000 000.  

 As the system.h is generated by SOPC builder and my SOPC shows the CPU connected to the External clock of 50 MHz, is this why the frequency is shown as 50 MHz in system.h despite the fact that this external clock is then multiplied by 2 in my main .v file? Is the CPU working at 50 MHz or 100 MHz?   If CPU is still working at 50 MHz, how do I get it to work at 100 MHz? I am thinking that instead of instantiating the altpll component obtained from Quartus MegaWizard in the main .v file, maybe I have to use the altpll component inside SOPC builder and then connect the output clocks to the CPU. Is that any good?  At the moment, I have everything in the .v file with pll sdram_pll neg_3ns (CLOCK_50, DRAM_CLK, system_clock);  and clk input to the NIOS as follows .clk (system_clock),

[Altera_Forum]

For the second paragraph, system.h file only tell you that your cpu should work at 50MHz, it only rely on your settings in SOPC Builder. If your cpu's input clock is not 50MHz, cpu can't working normally. 

 For the third paragraph, if you want your cpu working at 100MHz, just give it a 100MHz input clock, of course your cpu's clock settings should change to 100MHz in SOPC Builder.  I've never use the pll inside SOPC Builder, I hear from someone that it's not a good way.