Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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arria 10 use transciever phy ip

smile123
New Contributor I
1,469 Views

hi,everyone,i have a issue about transciever phy ip,as follows:

    the phy ip is 2 recieve channel,but the rx_is_lockedtoref  signal of ch1 is unstable, ch0 is ok.

    At the same time,i have a phy ip is 1 recieve channel to test the ch0 and ch1, all off them is ok,What is the problem?

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ZiYing_Intel
Employee
1,348 Views

Hi smile123,


When CDR is in locked to data mode, the status of rx_is_lockedtoref is unknown; it can be high or low or toggling. You do not need to care about rx_is_lockedtoref when rx_is_lockedtodata is high.


Regards,

zying


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FvM
Honored Contributor II
1,433 Views

Hi,
you agree that you are not giving much info about your design?
As a starter question, does your design meet timing? Do you see any warnings, e.g. related to PLL usage?

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smile123
New Contributor I
1,385 Views

Hi,it is sorry to reply to you now,my .qar project file is below.

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ZiYing_Intel
Employee
1,398 Views

Hi,


Thanks for submitting the issue. Allow me have some time to look into the issue and I will get back to you with findings.


Best regards,

zying


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ZiYing_Intel
Employee
1,398 Views

Hi smile123,


Can you share your .qar file here? So that I can try debug the issue from my side.


Best regards,

zying


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smile123
New Contributor I
1,385 Views

Hi,this is the .qar file.

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ZiYing_Intel
Employee
1,349 Views

Hi smile123,


When CDR is in locked to data mode, the status of rx_is_lockedtoref is unknown; it can be high or low or toggling. You do not need to care about rx_is_lockedtoref when rx_is_lockedtodata is high.


Regards,

zying


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smile123
New Contributor I
1,283 Views

ok,thank you for your reply。

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