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bootselect pins confusion

rshal2
New Contributor II
298 Views

Hello,

 

I am a bit confused with bootselect pins on arria V.

According to table A-1 from Arria V Device Handbook:

 

0x0 Reserved 0x1 FPGA (HPS-to-FPGA bridge) 0x2 1.8 V NAND flash memory 0x3 3.0 V NAND flash memory 0x4 1.8 V SD/MMC flash memory with external transceiver 0x5 3.0 V SD/MMC flash memory with internal transceiver 0x6 1.8 V SPI or quad SPI flash memory 0x7 3.0 V SPI or quad SPI flash memory

But in pins descriptions I see the following pins name (5ASXFB5H4F4):

SPIM0_SS0,BOOTSEL0 QSPI_SS0,BOOTSEL1 NAND_WE,BOOTSEL2

From this I understand that when bootsel2=1, it also enablse NAND ? If so, then why the 1st table only enables nand in 0x2,0x3 , i.e. only when bootsel1=1 ?

 

Thank you !

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4 Replies
sstrell
Honored Contributor II
50 Views

I think those names are the functions of the pins after boot (for example NAND_WE is NAND write enable) or if you're not using them for boot select. The 3 pins still use the BSEL encoding from the handbook.

 

#iwork4intel

rshal2
New Contributor II
50 Views

Thanks,

But I find it a bit strange, if they are boot selects pins, it means that they are connected to '0' or '1', not to other device.

So, how can such pin have both roles ?

 

Thanks

EBERLAZARE_I_Intel
50 Views

Hi,

 

I do not really get the question, correct me if I am wrong are you asking why there are two boot select pins for NAND devices?

EBERLAZARE_I_Intel
50 Views

Hi,

 

Do you have any followup from your side?

 

Regards.

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