can 2 72-bit DDR4 interfaces be placed on 10AX027 F34 device

[Jerry_Greenfield]

I am doing a design with the 10AX027H3F34E2SG.  We do not have a PCB yet, just working on figuring out the ideal pinout of the FPGA now before working too much on the PCB.   I have a 72-bit DDR4 interface connected to banks 3B, 3C, and 3D and compiling with no problem.  Additionally I have a 40-bit DDR4 interface connected to banks 2J and 2K and compiling with no problems.  I would like to expand the 40-bit DDR4 interface to a 72-bit DDR4 interface by connecting the additional 32 data bits, DM’s, and DQS’s to bank 2L, but I am having problems with this.  When I attempt to do a Place and Route the fitter gives me the following error:

Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Altera Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

               Error (175020): The Fitter cannot place logic pin in region (84, 97) to (84, 98), to which it is constrained, because there are no valid locations in the region for logic of this type.

                                        Info (14596): Information about the failing component(s):

                                                            Info (175028): The pin name(s): DDR4_DQ[64]

                                        Info (175015): The I/O pad DDR4_DQ[64] is constrained to the location PIN_L20 due to: User Location Constraints (PIN_L20)

                                                            Info (14709): The constrained I/O pad is contained within this pin

DDR4_DQ[64] is connected to bank 2L, pin L20 and is one of the new data signals I have added to the DDR4 interface.  According to column M of sheet “Pin List F34” of the 10ax027.xls file bank 2L contains DQ lanes 0 through 3 and should be a valid bank for DDR4 signals.  Is this true?  If so, do you have any idea what is causing this error?

Yesterday I came across the piece of documentation at the following web site:

https://www.intel.com/content/www/us/en/docs/programmable/683461/current/package-support-for-ddr4-x72-with-ecc-39715.html

This document says that the 10AX027 is only capable of supporting 1 72-bit wide DDR4 interface.  This appears to be what I am experiencing.  Is this really true, and if so why?  I already know that a 72-bit DDR4 interface can be placed in the bank 3 column, can an 72-bit DDR4 interface be placed in the bank 2 column, without using bank 2A?  It can be according to the 10AX027.xls pinout document.

I am using version 16.0,2 of Quartus because the design contains multiple IP cores that would be difficult to migrate to a new version of Quartus.

[AdzimZM_Intel · Accepted solution]

Hello,

For 10AX027 F34 device variant, the IO Bank 2L is supporting 3V I/O buffer type. Can check here: https://www.intel.com/content/www/us/en/docs/programmable/683461/current/gpio-banks-serdes-and-dpa-locations.html

For DDR4 interface, the IO Standard is configure to use POD12. And the POD12 IO Standard is not supported in 3V I/O Bank. Here the link for reference: https://www.intel.com/content/www/us/en/docs/programmable/683461/current/i-o-standards-support-for-fpga-i-o-in.html

That's make sense for the Quartus to show the errors about no valid locations in the region for the logic.

Regards,

Adzim

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.