can't boot from sram

[Altera_Forum]

I build sopc with epcs component, with the reset vector and exception vector at sram section, and set .text section at sram section, I have changed the sram width from 32 bit to 8 bit, but I still can't start program in sram when powered on. 

 How can I start program in sram when powered on?

[Altera_Forum]

Confirm if you have done these: 

- Reset vector for CPU in SOPC builder should point to EPCS - Add EPCS and SRAM as slaves to CPU data master and instruction master   Satish

[Altera_Forum]

hi, Satish. The program can run without sram or sram just used for storing data. 

When I want boot copier to load boot section onto sram, it does't work.  I do an experiment that sopc just with on chip memory and EPCS, pio, cpu. I set reset vector and exception vector to on chip memory, it works. but I set these vector to EPCS, it does't work when power on. just work after debug with JTAG.  Did any one have experience that boot with sram? When program bigger and bigger, the .text section can't be set to on chip memory, I found some reference said that the program can boot with CFI(.text set to CFI), but CFI is not fast enough, I think there be a method let the program boot on SRAM , of course, the program stored in EPCS or CFI.

[Altera_Forum]

Hi Sailor! 

 Are you programming your EPCS with the software (and hardware, for that matter) after setting the reset vector there? That's what must be done with EPCS or CFI (serial and parallel) flash devices.  After that everything should work.  Cheers,  --slacker

[Altera_Forum]

Hi  

 I am having similar problems. I have run out of on chip memory space on my cyclone I device and so I need to be able to boot my software from my volatile SRAM after power cycle.  I'm not clear on exactly what i need to do to do this. So far i have been setting the reset vector to the EPCS and exceptions to on-chip RAM in sopc builder and in NIOS IDE my BSP linker list i have changed all the linker sections (except the grayed .entry and .exceptions) to my SRAM.  If i upload my newly compiled .sof in quartus via jtag everything works? but if i upload to EPCS to run without jtag it only appears to retain the hardware design and not the software?? I need them both to be there on power cycle.  Does anyone have experience of making this work and is it possible to do this?  Jockeyjim

[Altera_Forum]

you have two images to flash on the EPCS. First the .sof file that contains the hardware, and then the .elf file that contains the software. 

The bootloader included in the EPCS controller will read from the EPCS flash, jump over the hardware image and copy the .elf file contents to the SRAM. To flash the .elf file in the EPCS you can use the nios programmer.

[Altera_Forum]

Thanks Daixiwen 

 I should have said that i have tried the following programming procedure:  using quartus programmer Uploaded the .sof with JTAG  The hardware (and software? maybe stays on from last time the elf was loaded) appear to work fine at this stage  with power still on i then......  using nios flash programmer Uploaded the .sof (sof2flash) with JTAG The hardware is now non volatile and works after power cycle but fails to run software Uploaded the .elf (elf2flash) with JTAG The hardware software now work on soft reset but after a power cycle it appears that the hardware is gone and with logic elements not generating expected activity on the boards LED's and consequently no CPU activity.  Jockeyjim

[Altera_Forum]

What version of Quartus are you using? There are several versions that have bugs with the elf flashing part.

[Altera_Forum]

Quartus is 9.1 sp2 

 and   Eclipse Platform Version: 3.4.1 Build id: M20080911-1700 with Nios II 9.1 Software Build Tools

[Altera_Forum]

Then I think you have the bug. Have a look at this thread: http://www.alteraforum.com/forum/showthread.php?t=22441 

There was an EPCS boot problem on Quartus 9.0, that was fixed in a service pack. It appeared again on Quartus 9.1, fixed in SP1, appeared again in SP2, and fixed in 10.0

[Altera_Forum]

I have tried the latest version 10sp1 and also tried the procedure shown on the rd04112006_450.html solution page but i'm still having problems 

 This solution includes a sof2flash step but the flash file is not used? i don't understand this? Also, the nios2-elf-objcopy won't run unless you have -- proceeding input-target and output-target  I go on to create the hex file from the elf and then convert the programming file to a .pof which i am struggling to reliably upload without getting a device id error. When i have managed to do upload it it hasn't run. Do i need to point the on-chip rom to this hex file?  J

[Altera_Forum]

the "sof" flash is just used to know where to place the elf application in the EPCS. It should be placed right after the hardware configuration. 

I find the mathed they describe a bit complicated... Using the Nios programmer you can directly write both .flash files in the EPCS.

[Altera_Forum]

Thats the method i have been using. 

 Could this be a memory mapping issue?

[Altera_Forum]

I've just managed to get it to work by adding the .sof and .elf files in the flash programmer at the same time. At least i think thats why it now works! Before i had uploaded them one after the other with possibly a soft reset in between. 

 I hope this was not just a fluke!

[Altera_Forum]

In theory you should be able to flash them separately, as long as the two generated .flash files were made from the same .sof source (and with the same settings, especially compression for the hardware image). But I'm glad you found a way that works ;)

[Altera_Forum]

I'm sure i tried that with 9.1sp2, so maybe it is the version specific bug! 

 Thank you for you help Daixiwen.  Jockeyjim