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clock divider

Altera_Forum
Honored Contributor II
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Hi, how can I divide the 50 mhz clk to 33.2 mhz clk in vhdl code?

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Altera_Forum
Honored Contributor II
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Have you tried the PLL thingy. That is one option, the other being a clock enable at a rate of 332/500 or 83/125 of the 50 MHz clock (modulo adder). 

Thus you bash your flips on 50MHz but slow them down at enable rate.
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Altera_Forum
Honored Contributor II
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Thanks for your response!:)

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Altera_Forum
Honored Contributor II
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You better use a modulo adder e.g. add 83 modulo 125 and generate clk en at overflow. 

You may try this code, I haven't tested it but I will appreciate if you do and let me know the outcome: 

 

variable count : integer range 0 to 124 := 0; process begin wait until clk50mhz = '1'; if count < 125 then count := count + 83; clken <= '0'; else count := count - 125; clken <= '1'; end if; end process;
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Altera_Forum
Honored Contributor II
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I second Kaz on this, with a minor modification. I have always used a modulo counter for clock division. So you can use a counter to count the cycles, thus increase it by one each cycle, and once a value is reached, set the clock high. In this way you won't need the adder and subtractor in Kaz's code (incrementor is cheaper in terms of HW).

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

I second Kaz on this, with a minor modification. I have always used a modulo counter for clock division. So you can use a counter to count the cycles, thus increase it by one each cycle, and once a value is reached, set the clock high. In this way you won't need the adder and subtractor in Kaz's code (incrementor is cheaper in terms of HW). 

--- Quote End ---  

 

 

Hi turhank,  

you can count cycles and then raise clken if you are dividing by integer. but in our case it is fractional 83/125 so you can't count 125 of clcok and generate 83 clk en. The modulo adder is itself doing the division of 83/125
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Altera_Forum
Honored Contributor II
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I see what you mean. Thanks for the clarification.

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Altera_Forum
Honored Contributor II
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However you can count 125 clocks then output 83 clocks withing each 125 as high enable. But I prefer to have it as spread as possible

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Altera_Forum
Honored Contributor II
748 Views

I used the pll and I get my result. I think the alt-pll is very easy and more accurate.

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