clock structure?

[Altera_Forum]

The cyclone ii fpga handbook says it has 4 built in PLLs. Are these associated with a particular input pin on the device? Is one of the main advantages of using a PLL on a clock input to increase accuracy in a system with noise? 

 It also talks about upto 16 clock input pins for global clocks. How do these differ from the 4 PLLs?  What is to stop me from using just any random Input pin as my clock input?

[Altera_Forum]

Please consult the devive manual. The clock managment chapter is answering your question in detail (at least most of it). 

 As a brief answer, each PLL has associated clock inputs. With Cyclone II, a PLL must be exclusively clocked by one of it's associated inputs. So feeding an external clock to only one input implies, that you can only use one PLL in the design. This restriction has been removed with successor chips.    --- Quote Start ---  Is one of the main advantages of using a PLL on a clock input to increase accuracy in a system with noise?  --- Quote End ---   Not particularly. It's intended for clock synthesis, mainly generation of high clock frequencies and multiple phase locked clocks. They are needed e.g. for DDR RAM controllers or high speed serial interfaces. But PLL's rather increase the device susceptibility to noise than making it operating more reliable. The analog PLL supply of Cyclone II (VCCA) must be carefully bypassed to avoid problems of PLL loose of lock in presence of supply interferences. Also the clock signal quality is more critical when using PLLs.

[Altera_Forum]

ok thanks.  

 so if I have a design in which the clock is routed into a general I/O pin (not one of the 16 clock pins), but do not need to use the PLL, will this be problematic?

[Altera_Forum]

Yes, you may have trouble achieving timming closure with that. 

If possible, use one of the dedicated clock input pins.  The general I/O pins can't drive the global (low skew) clock networks directly, so the clock signal will be distributed using the generic fabric, which will lead to high skew.  This can be somewhat remedied by insering a LCELL primitive between the clock signal from the pin and the clock signal actually used to drive the logic within the FPGA -- the output of the LCELL can be routed though a global clock network. This mostly fixes the problem for the logic within the FPGA.  But even so, due to the delay between the I/O pin and the LCELL output, it can be difficult to achieve I/O timming closure.

[Altera_Forum]

ok. i don't think i would have easily interpreted all of that out from the Handbook being that im new to altera and fpga. thanks again.