clocks on logic analyzer

[Altera_Forum]

I have a pll, a NCO block on my system. I am trying to verify the design on signaltap logic analyzer. The input to the pll, is the 50 MHz on-board oscillator. I used this on board oscillator as the acqusition clock in the signaltap logic analyzer. The ppl generated clock shown on the logic analyzer is wrong. How do you go about on using this signal tap? And those time units, they are just wrong?

[Altera_Forum]

How do you know its wrong? whats the expected frequency? unless it is less than 25Mhz how do you expect signal tap to capture the clock correctly. Even at 25MHz you are probably not going to get a decent reading.

[Altera_Forum]

I know it is wrong because I used the time bars to measure the time difference and translated that to frequency. I divided the on-board 50 MHz by 10, so I am expecting 5 MHz. But I get some clock in the range of Hz. When you say how I expect signaltap to capture the clock correctly what do you mean? How does signaltap work?

[Altera_Forum]

Signal tap is not an ocilloscope, it is a logic analyser, so each "dot" is a single data sample. Each sample is 20ns. With a 5MHz output clock, the output clock should be high for 5 samples and low for 5 samples.

[Altera_Forum]

Thanks Tricky, will check it out again.

[Altera_Forum]

HELP !!!!!!!!!!!! 

 I am using the fft megacore function in streaming mode. I have set the reset_n pin and sink valid at the same time. In the next clock cycle i assert the sink_sop for one clock cycle(It is only active for one clock cycle). At the point where I assert the sin_sop, that is where the FFT block asserts the sink_ready. And I do not get a source_error, but there is no output. It is zero all the time. My sin_imag is zero. That is I am only inputing the real signal.

[Altera_Forum]

please file a new thread on your FFT question

[Altera_Forum]

how do i start a new thread