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Valued Contributor III
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combinational logic path timerequest slack

Hi, 

I encounter a time slack problem. In timequest i find the path between two registers is two long ,there are too many levels of combintional logic .so i locate the path in the technology map viewer ,but the register is tranlated to bottom level ,and i can't correspond it with the code ,and the code is too complex to understand ,so i want to know there is any good idea to break up the combinional logic path and how to insert register to improve time slack.:confused: 

 

thanks first!
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Valued Contributor III
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Re: combinational logic path timerequest slack

Not sure what you mean by it being translated to the bottom level. That is the place where it is coded, as there is no higher level translation. If you're going to insert pipeline registers, you have to understand the code, there's no way around that. Maybe the RTL viewer will help decipher it? 

Are you using some high-level HDL generation tool? QSYS, Advanced DSP Builder or something like that? There is certainly a difficulty in understanding the low-level HDL, and most fixes for any issues here need to be done at the high-level.
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Valued Contributor III
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Re: combinational logic path timerequest slack

One thing you might try is to add a pipeline register back-to-back with one of the registers in the path (with nothing in between), and then turn on Register Retiming, one of the features of Physical Synthesis (under Settings -> Compilation Process Settings). The tool will then move one of the registers into the combinatorial logic path if it is possible.

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Valued Contributor III
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Re: combinational logic path timerequest slack

 

--- Quote Start ---  

Hi, 

I encounter a time slack problem. In timequest i find the path between two registers is two long ,there are too many levels of combintional logic .so i locate the path in the technology map viewer ,but the register is tranlated to bottom level ,and i can't correspond it with the code ,and the code is too complex to understand ,so i want to know there is any good idea to break up the combinional logic path and how to insert register to improve time slack.:confused: 

 

thanks first! 

--- Quote End ---  

 

 

Direct breaking of long paths is purely a design issue, here is an example:  

You want to saturate data1(signed 9 bits) to data2(signed 8 lsb bits) by discarding 1 msb. 

 

-- clocked process, not tested if data1(8 downto 7) = "00" or data1(8 downto 7) = "11" then data2 <= data1(7 downto 0); elsif data1(8 downto 7) = "10" then data2 <= "11111111"; else data2 <= "100000001"; end if;  

 

to break above path shorter, you precompute the required flags using intermediate registers: 

-- clocked process, not tested if data1(8 downto 7) = "00" or data1(8 downto 7) = "11" then flag1 <= '1'; else flag1 <= '0'; end if; if data1(8 downto 7) = "10" then flag2 <= '1'; else flag2 <= '0'; end if; if data1(8 downto 7) = "01" then flag3 <= '1'; else flag3 <= '0'; end if; data1_d <= data1(7 downto 0); if flag1 = '1' then data2 <= data1_d; elsif flag2 = '1' then data2 <= "11111111"; elsif flag3 = '1' then data2 <= "10000001"; end if;  

 

Thus 3 extra intermediate registers are added to break the single path into two sections, also adds one delay to final output. 

In the first method there is one cloud of logic between two registers(data1 & data2). 

In the second method this cloud is broken into 3 smaller clouds between data1& flag1/flag2/flag3 then followed by another small cloud between flags & data1_d
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