Hi everyone!
I've created a project to test test lpm module. The simulation seems strange to me. The output of the lpm_rom has one clock period delay.
For example, address 00 has content of "AEFF", 01 "BD11", 02 "CD12" etc, when the first rising edge of lpm_rom's clock comes, the output is not what expected "AEFF", it's
"0000"; current address 02, but on the rising edge of clock, output is address "01"'s content, "BD11"!
Seems to me it always gets the previous address content instead of current one!
I've attached the design files, can someone explain it?
// cnt4bit.v
// address generator
module cnt4bit(clk, rst, addr);
input clk, rst;
output [3:0] addr;
reg [3:0] addr;
always @( posedge clk or posedge rst)
if(rst==1)
addr <= 4'b0;
else
addr <= addr + 1'b1;
endmodule
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