링크가 복사됨
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
It can't be done in that direction. If you want a graphical view of VHDL code, you can use the RTL viewer after synthesis. But it's not always easy to read
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
My question is how to create a project made in vhdl code in a block schematic representation......it can't be made by do create/udate->create ymbol files for current fle?
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
--- Quote Start --- My question is how to create a project made in vhdl code in a block schematic representation......it can't be made by do create/udate->create ymbol files for current fle? --- Quote End --- Hi, as Daixiwen mentioned it is not possible to convert a project written in VHDL into a schematic. Why do you want a schematic ? Only to get an overview of the struture of your design? As Daixiwen mentioned you can use the RTL viever of Quartus for that purpose. Kind regards GPK
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
Iam making a bigger project in block diagram schematic file form and i want to add this .vhd project file to it....
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
In that case yes you can right click on the vhdl file in quartus and select "Create Symbol Files for Current File". It will create a bsf file that is a block you can add to your block diagram schematic file.
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
--- Quote Start --- Iam making a bigger project in block diagram schematic file form and i want to add this .vhd project file to it.... --- Quote End --- Hi, then create a symbol of your VHDL project and instanciate it in your schematic: File -> Create/Update -> Create Symbofile for current file This option is only active when you open the designfile ! I have a small project attached. It uses Verilog, but there is no difference for Symbol generation. Kind regards GPK
- 신규로 표시
- 북마크
- 구독
- 소거
- RSS 피드 구독
- 강조
- 인쇄
- 부적절한 컨텐트 신고
When I try this conversion from vhdl to bsf (symbol) the file>create/update has all menu entries are greyed out (not selectable). What is the trick to creating a symbol?
