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--- Quote Start --- My question is how to create a project made in vhdl code in a block schematic representation......it can't be made by do create/udate->create ymbol files for current fle? --- Quote End --- Hi, as Daixiwen mentioned it is not possible to convert a project written in VHDL into a schematic. Why do you want a schematic ? Only to get an overview of the struture of your design? As Daixiwen mentioned you can use the RTL viever of Quartus for that purpose. Kind regards GPK
In that case yes you can right click on the vhdl file in quartus and select "Create Symbol Files for Current File". It will create a bsf file that is a block you can add to your block diagram schematic file.
--- Quote Start --- Iam making a bigger project in block diagram schematic file form and i want to add this .vhd project file to it.... --- Quote End --- Hi, then create a symbol of your VHDL project and instanciate it in your schematic: File -> Create/Update -> Create Symbofile for current file This option is only active when you open the designfile ! I have a small project attached. It uses Verilog, but there is no difference for Symbol generation. Kind regards GPK
