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Valued Contributor III
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different width dual port ram from VHDL template

Dear all, 

In my design I have a dual port memory, where the write port is 128x32 configuration and read port is 4096 x 1. I have written the module in the VHDL, but my implementation results in instauration of dual port memory with both ports having 32bits and lots of glue logic around. 

 

When instantiating via megawizard, iget both ports cpnfigured correctly. That brings me a question: 

 

1. What is the proper VHDL template to instantiate different bus width memory 

 

2. How can i te-l to compiler, that this particular entity must be different bus width 

 

3. Is there a way how to tell to compiler to instantiate such memory into m4k memory 

 

4. Itseems that such memory configuration can be write-through instead of pipelines. How that changes the VHDL template? 

 

As for 4. I'm asking because i have some fancy feeling, that when simulating the design, the simulator sometimes simulates the memory as write-through, whereas another times as pipelined. 

 

The relevant piece of code is here. It contains as well some logic calculating number of bits set to 1 in all the memory. This is however irrelevant to issues asked here 

 

http://svnweb.cern.ch/world/wsvn/fimdab/trunk/vhdl/fpga/sources/bunch_selection_memory/bunch_selecti... 

 

Thanks for any comment 

 

David
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Valued Contributor III
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I think I've found some answers (about how to instantiate mix-width dpram) in here: 

 

Recommended HDL Coding Styles, Quartus II 10.1 Handbook - Altera
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Valued Contributor III
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Just a word of warning. variable bitwidth demands too much memory blocks especially if it is read/write on both ports, check your resource and you will see.

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Valued Contributor III
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--- Quote Start ---  

 

In my design I have a dual port memory, where the write port is 128x32 configuration and read port is 4096 x 1. I have written the module in the VHDL, but my implementation results in instauration of dual port memory with both ports having 32bits and lots of glue logic around. 

 

--- Quote End ---  

 

 

I'd recommend keeping both ports with the same widths, and then just implementing your own serializer logic on the 1-bit side, i.e., read a 32-bit value and serialize it as 1-bit data. 

 

Cheers, 

Dave
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Valued Contributor III
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but why that? If the serializer logic forms a part of the m4k cell, there should be advantage of using the onchip logic rather than generating my own. If you see in the code attached, i have implemented sort of serialization, but it generates quite a lot of logic around the memory cell itself.  

 

N.b. i still did not find any method how to tell to compiler via tcl commands to instantiate that entity as m4k cell. Whereas when using megawizard on one of the screens it asks you into which memory you want to implement it. Afaik this is quite important as I've read in one of altera documents that m4k memory registers writes on falling edges of write signal. I just hope that I did not understand correctly and this behaviour is only for asynchronous memories, which is not my case
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Valued Contributor III
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I am in need of higher clock more than 600MHz.... In Altera Fpga kit it has an internal clock upto 50Mhz. If i use any external clock source, which is going to be compatible? function generator or crystal oscillator. Is Crystal oscillator alone is enough to form the external clock

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Valued Contributor III
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--- Quote Start ---  

but why that? If the serializer logic forms a part of the m4k cell, there should be advantage of using the onchip logic rather than generating my own. If you see in the code attached, i have implemented sort of serialization, but it generates quite a lot of logic around the memory cell itself.  

--- Quote End ---  

 

 

I have never heard of dedicated memory blocks having their own logic. Any logic needed will be borrowed from the fabric in both cases whether you infer by template or use lpm. 

 

The question of serialising seems vague to me in its purpose. I assumed you need two different widths so that you can read all 4096 bits in one clock. Otherwise there is no need to make it that wide.
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Valued Contributor III
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Templates to infer dual port RAM with ports of different width can be found in the Quartus Software Handbook. I don't see a reason to doubt it's correct operation, although I implemented similar design previously by instantiating altsyncram in my VHDL code directly (I didn't know how to infer it). The selection of different RAM types by synthesis attributes is also discussed in the Software Handbook. 

 

 

--- Quote Start ---  

variable bitwidth demands too much memory blocks especially if it is read/write on both ports, check your resource and you will see. 

--- Quote End ---  

 

As long as the implemented bitwidths are within the supported range of the respective RAM type, there should be not a single RAM cell wasted. At least I didn't observe this in my RAM designs. 

 

--- Quote Start ---  

but why that? If the serializer logic forms a part of the m4k cell, there should be advantage of using the onchip logic rather than generating my own. 

--- Quote End ---  

 

Yes, that's why the different width feature is offered by Altera.
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Valued Contributor III
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--- Quote Start ---  

 

 

As long as the implemented bitwidths are within the supported range of the respective RAM type, there should be not a single RAM cell wasted. At least I didn't observe this in my RAM designs. 

 

 

--- Quote End ---  

 

 

It depends what is meant by "support". I had a design of ram in stratix IV as follows: 

portA: 16bits x 256 

portB: 512bits x 8 

 

resource required: 140 M9Ks !!! if read/write on both ports but reduced to 20 M9Ks if write only/read only. 

 

The issue of intrinsic block support is not always visible to the user. Ofcourse if the block is made to support the width there would be no waste. It is when it does not and the tool does not tell.
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Valued Contributor III
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--- Quote Start ---  

but why that? If the serializer logic forms a part of the m4k cell, there should be advantage of using the onchip logic rather than generating my own. 

 

--- Quote End ---  

You did not mention the device or memory type in your post. I would recommend using Modelsim to simulate the memory. 

 

 

--- Quote Start ---  

 

i still did not find any method how to tell to compiler via tcl commands to instantiate that entity as m4k cell. Whereas when using megawizard on one of the screens it asks you into which memory you want to implement it. Afaik this is quite important as I've read in one of altera documents that m4k memory registers writes on falling edges of write signal. I just hope that I did not understand correctly and this behaviour is only for asynchronous memories, which is not my case 

--- Quote End ---  

I have not seen Tcl commands for controlling the RAM inference. Rather, I use the MegaWizard to generate a template, and then copy and edit its internal instantiation of the altsyncram component. 

 

Cheers, 

Dave
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Valued Contributor III
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I think what is missing from this discussion is how a block of ram is designed to support variable width.  

 

My view is that a ram block and depending on device will support a list of width Vs size and I know for example stratix iv M9Ks support up to 36 bits width... how? possibly through some extra logic inside ram block itself.  

Any more width request requires that several blocks are aligned together plus extra logic from fpga fabric to bridge across the two different widths, say logic from short side muxed into wider bus then connected to all ram blocks in parallel. This is where substantial ram waste may occur.
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Valued Contributor III
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Well, this is of course the approach. But instantiating using megawizard renders the design not generic so when porting to xilinx this will require some additional work c whereas when written in pure VHDL, this step can be omitted. Unfortunately in my case the chance to swap the design to xilinx is slightly probable. In addition, Iprefer to write pure VHDL rather than using device specific stuff. 

 

Currently this design is built for stratix, this one has trimatrix. these are reasons for finding a way how to write generic VHDL. If I'd be able to specify in quartus setting file that particular entity is the m4k cell, that would be great. 

 

I've tried to use VHDL piece of code written in coding handbook to instantiate different bus width memory.this seems to work. still, it can be instantiated into m4k or higher. For the moment I'm letting quartus to decide what memory block it should use. Seems that its decision for the moment conforms with mine. 

 

D. 

 

 

 

--- Quote Start ---  

You did not mention the device or memory type in your post. I would recommend using Modelsim to simulate the memory. 

 

I have not seen Tcl commands for controlling the RAM inference. Rather, I use the MegaWizard to generate a template, and then copy and edit its internal instantiation of the altsyncram component. 

 

Cheers, 

Dave 

--- Quote End ---  

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Valued Contributor III
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--- Quote Start ---  

Well, this is of course the approach. But instantiating using megawizard renders the design not generic so when porting to xilinx this will require some additional work c whereas when written in pure VHDL, this step can be omitted. Unfortunately in my case the chance to swap the design to xilinx is slightly probable. In addition, Iprefer to write pure VHDL rather than using device specific stuff. 

 

--- Quote End ---  

I also prefer portable VHDL, however, we don't live in a perfect world :) 

 

You can write code that can be re-targeted to Xilinx devices, or other memory types within the Altera device family by creating your own RAM component (port definitions). You can then use a VHDL configuration to map that component to an actual RAM device. 

 

This allows you to keep most of your code general purpose. 

 

I wrote a set of examples called vhdl_configurations.zip available at this thread: 

 

http://www.alteraforum.com/forum/showthread.php?t=30414&highlight=vhdl_configurations.zip&page=2 

 

Cheers, 

Dave
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