Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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do the intel fpga need a global reset signal or not ? If needed, the reset signal should be input using special IO pin or not?

zlan01
Beginner
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can general IO pin be used to input the reset signal ?

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skyjuice
Employee
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Quartus will decide whether or not to promote the reset to use Global network based on several factors (i.e fanout). You can internally generate a reset source. If you decide to use an input pin, make sure to synchronize them to avoid metastability issue.

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