epcs does not configure cyclone V

[Altera_Forum]

Hello, 

my ecps on my board does not configure my fpga. I create a jic file and programm the epcs.This works ok. But my programm does not boot. With the nios2flash programmer i can convert sof2flash and elf2flash and programm the epcs,but it still not configure my fpga.  On my design board i have the vccbat at 1.8V? Is that the problem? I've seen in reference design that this Voltage is set to 2.5V.  Has someone the same problem and can help?  Thanks. Sacko

[Altera_Forum]

Hi,  

 Did you set the configuration scheme to Active Serial in the "device and pin option" setting in Quartus II? Make sure the settings in the Quartus II are correctly set for AS mode.

[Altera_Forum]

Also you may try to disable the EPCS/EPCQ ID check when generating the .jic file. 

Go to the Advance button in the Convert Programming File utilities, then turn on the "Disable EPCS/EPCQ ID check" option.

[Altera_Forum]

Hello nyusof, 

 thanks for your quick answer. 1) yes i have set the configuration scheme to Active serial 2)i did also disable the EPCS ID but it still not the same. It is not a problem of silicon ID.The silicon ID has been recognized. I have controlled my design again and check the signals with an oscilloscop. +After programming the EPCS the nstatus line and the conf_done line still be low. +After powerup the EPCS chip select NCS remain high and the clock SCL low.  thanks.

[Altera_Forum]

That suggests to me the MSEL pins are not set correctly. If you're not seeing any activity DCLK and nCS remains high I'd suggest that's the place to start. If you think they're correct check the board's assembled properly and that the pins are soldered down. 

 Check you're not holding nCONFIG low and that nCE is tied or connected directly to GND. Check all power pins are powered.  Once the POR circuit is happy and the POR delay has completed configuration should begin. I suspect the POR circuit is happy since you're able to program the EPCS. If it wasn't you wouldn't be able to access the FPGA via JTAG either.  Given you can program the EPCS it should be something pretty simple.  Cheers, Alex

[Altera_Forum]

Please check the Active Serial source clock is set to either 100Mhz, 50Mhz or 12.5Mhz in the Device and Pin Option settings in Quartus II. If the clock is set to CLKSR, the FPGA will expect external clk input to generate the DCLK.

[Altera_Forum]

nyusof, 

 Changing those settings only affects the resulting configuration bitstream (.sof). So, any changes made there will only take effect once the configuration process starts - which, in AS mode, depends on nCE & DCLK. They, in turn, are dependent on the MSEL settings and the POR and little else.  So, if you have no activity on nCE or DCLK you need to look at your board and not your Quartus settings.  Cheers, Alex

[Altera_Forum]

thanks for your suggestions. 

The quartus settings are all ok. The MSEL[3..0] are set to AS Standard(10011) i will look at my board .It must be something wrong at there. Thanks

[Altera_Forum]

--- Quote Start ---  thanks for your suggestions. The quartus settings are all ok. The MSEL[3..0] are set to AS Standard(10011) i will look at my board .It must be something wrong at there. Thanks  --- Quote End ---    an error from me: MSEL is a 5 Bit of course.  Could VCCBAT be a problem when sets to 1.8V?   thanks,

[Altera_Forum]

VCCBAT range is 1.2V to 3.0V. So, 1.8V is fine (although not exactly in line with a note in the datasheet). It states: 

--- Quote Start ---  If you do not use the design security feature in Cyclone V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. Cyclone V power-on reset (POR) circuitry monitors VCCBAT. Cyclone V devices do not exit POR if VCCBAT is not powered up.  --- Quote End ---    Cheers, Alex