gate level simulation error

[Altera_Forum]

Hi all, 

i have a problem in gate level simulation. actually i have two kits  1- cyclone IV gx EP4CGX150DF31C7 kit 2- SDALTEVK (ti) sdi kit.  both kits can be connected through HSMC, during pin planning, i configure sdaltevk hsmc connection to cyclone iV hsma. after that i got some error which is as. Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 321 of differential I/O pin 'tx_d_p[1]' in pin location K26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 322 of differential I/O pin 'tx_d_n[2]' in pin location J26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 325 of non-differential I/O pin 'genlock_no_ref' in pin location D29 is too close to pad 320 of differential I/O pin 'tx_d_n[1]' in pin location K27 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 320 of differential I/O pin 'tx_d_n[1]' in pin location K27 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 321 of differential I/O pin 'tx_d_p[1]' in pin location K26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 322 of differential I/O pin 'tx_d_n[2]' in pin location J26 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 324 of non-differential I/O pin 'genlock_no_lock' in pin location D30 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 4 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 329 of non-differential I/O pin 'sdi_ck_sel0' in pin location C29 is too close to pad 331 of differential I/O pin 'tx_d_n[3]' in pin location H25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 329 of non-differential I/O pin 'sdi_ck_sel0' in pin location C29 is too close to pad 332 of differential I/O pin 'tx_d_p[3]' in pin location J25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 331 of differential I/O pin 'tx_d_n[3]' in pin location H25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 332 of differential I/O pin 'tx_d_p[3]' in pin location J25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug. Error (169079): Pad 328 of non-differential I/O pin 'sdi_ck_sel1' in pin location C30 is too close to pad 323 of differential I/O pin 'tx_d_p[2]' in pin location K25 -- pads must be separated by a minimum of 5 pads. Use the Pad View of Pin Planner to debug. Error (168002): Live I/O check failed   check attached schematic for both kits and then give me solution what can i do fir this ??

[Altera_Forum]

Add an "IO_MAXIMUM_TOGGLE_RATE" attribute, to each of the non-differential signals listed, and set it to "0 MHz". You can do this through the Pin Planner (enter "0" [zero] in the 'Toggle Rate' column for the relevant signal) or directly in the .qsf. You should end up with a .qsf entry, for each signal, similar to:set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to genlock_no_ref 

Looking at the names of all your culprit signals, this attribute looks to be valid.  Cheers, Alex

[Altera_Forum]

HI Alex, 

  this for your ans, it really works for me.  after this i have new error while programming file generation.  Internal Error: Sub-system: ASMDB, File: /quartus/db/asmdb/asmdb_mux.cpp, Line: 363 ASMDB_MUX error: ENCODED_MUX::select : index out of range (index = 16, size = 16) : last archgroup encountered: type = PLL_VOLTAGE_REGULATOR_STINGRAY, block_type = GENERAL_PLL Stack Trace:  0x2826a: ASMDB_MUX::internal_error + 0x83a (db_asmdb)  0x28611: ASMDB_ENCODED_MUX::select + 0x61 (db_asmdb)  0x13a33: ASMDB_ARCH_GROUP_STD::select + 0x153 (db_asmdb)  0x1e578: ASM_ARCH_GROUP::mux_select + 0xd8 (comp_asmcc)  0x1289d8: ASM_LAB_BITS::get_row_size + 0x9e08 (comp_asm)  0x20577f: ASM_AVALON_SPACE::operator= + 0x121f (comp_asm)  0x207444: asm_process_sof + 0xb04 (comp_asm)  0x20a511: asm_process_sof + 0x3bd1 (comp_asm)  0x20d451: asm_assemble + 0x3e1 (comp_asm)    0x12718: QEXE_ARGS::get_command_line + 0x1ca8 (comp_qexe)  0x15a7a: qexe_process_cmdline_arguments + 0x5aa (comp_qexe)  0x15b91: qexe_standard_main + 0xa1 (comp_qexe)    0x4e88: msg_exe_fini + 0x58 (CCL_MSG)  0x56cc: msg_exe_fini + 0x89c (CCL_MSG)  0x1614: MEM_SEGMENT_INTERNAL::~MEM_SEGMENT_INTERNAL + 0x1a4 (ccl_mem)  0x62ff: msg_exe_main + 0x8f (CCL_MSG)    0x1652c: BaseThreadInitThunk + 0xc (kernel32)  0x2c520: RtlUserThreadStart + 0x20 (ntdll)   End-trace   Quartus II 64-Bit Version 12.1 Build 243 01/31/2013 SJ Web Edition Service Pack Installed: 1  what i do for this ??

[Altera_Forum]

That is a crash. You need to try a different version or raise a support ticket with altera.

[Altera_Forum]

hi, 

before i am using 12.1 SP1 and now i am using 15.1 after update tool this error again comes. what we do next ?

[Altera_Forum]

--- Quote Start ---  hi, before i am using 12.1 SP1 and now i am using 15.1 after update tool this error again comes. what we do next ?  --- Quote End ---    Like I said - it is a crash - you need to raise a case via altera mysupport

[Altera_Forum]

My question would be why are you running gate level simulations to begin with?