generate problem

[Altera_Forum]

Hi friends, 

 I try to replicate a module by N (parameter) times. Each small instance is connected (wire) with prev and next. In original design (fixed 8 cells) I just declared 8 wires  wire out7, out6, out5, out4, out3, out2, out1, out0;  But how can I do now when I am (try to be) parametrized?   generate   for ( i = 0; i <= N-1; i = i+1 )  begin: inst    shiftcell (    .Load(Load),  .Clock(invSCK),  .Din(DataIn[i]),   .Prev(Serial_In),   .Dout(out7)   );    end  endgenerate  For out7 wire name I need somehing like out{i}. Thanks very much for help in advance.

[Altera_Forum]

Obviously, you need to declare your wire variable as a vector.

[Altera_Forum]

Perhaps zuzu22 wants to say that he is constrained to use out7 from the external design. 

 He can generate the architecture using out[7] but he then needs a module that translate these signal inputs in out7.  It seems that he wants to "construct" the name of the signal using "i".  I don't know how to solve the problem, however.

[Altera_Forum]

Thank you very much FvM, it worked nice. A small problem now 

 Critical Warning (10846): Verilog HDL Instantiation warning at shifterNmsb.v(45): instance has no name  wire w[N:0]; // N+1 wires  generate   for ( i = 0; i <= N-1; i = i+1 )  begin: inst    shiftcell (    .Load(Load),  .Clock(invSCK),  .Din(DataIn),   .prev(w),   .Dout(w[i+1])   );     end  endgenerate

[Altera_Forum]

--- Quote Start ---  instance has no name  --- Quote End ---   True indeed. Something like shiftcell shiftcell_inst ()

[Altera_Forum]

Oukey, thanks again, solved (without underscore) 

  shiftcell inst (    );   Best regards,