pin assignment problems,help!

[Altera_Forum]

quartus ii shows the following error: 

Error: Output or bidirectional pin out_port_from_the_led_pio[1] in pin location P12 (pad_105) is too close to VREF pin in pin location T11 (pad_106)  Error: Can't place VREF pin T6 (VREFGROUP_B3_N0) for pin mem_dqs_to_and_from_the_ddr_sdram[1] of type bi-directional with SSTL-2 Class I I/O standard at location T8.  Error: Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 3 when the VREF pin T6 (VREFGROUP_B3_N0) is used on device EP3C25F324C8 -- no more than 9 output/bidirectional pins within 12 consecutive pads is allowed when voltage reference pins are driving in, but there are potentially 10 pins driving out.  Info: Location U5 (pad PAD_73) : Pin mem_addr_from_the_ddr_sdram[1] of type output uses SSTL-2 Class I I/O standard  Info: Location P8 (pad PAD_78) : Pin mem_addr_from_the_ddr_sdram[4] of type output uses SSTL-2 Class I I/O standard  Info: Following 7 pins have the same output enable group 2113154281: 6 pins require VREF pin and 7 pins could be output.  Info: Location U3 (pad PAD_68) : Pin mem_dqs_to_and_from_the_ddr_sdram[0] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location V3 (pad PAD_69) : Pin mem_dm_from_the_ddr_sdram[0] of type output uses SSTL-2 Class I I/O standard  Info: Location U4 (pad PAD_71) : Pin mem_dq_to_and_from_the_ddr_sdram[0] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location V4 (pad PAD_72) : Pin mem_dq_to_and_from_the_ddr_sdram[1] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location V5 (pad PAD_74) : Pin mem_dq_to_and_from_the_ddr_sdram[3] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location R8 (pad PAD_76) : Pin mem_dq_to_and_from_the_ddr_sdram[2] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location P9 (pad PAD_79) : Pin mem_dq_to_and_from_the_ddr_sdram[4] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Following 1 pins have the same output enable group 1191024410: 0 pins require VREF pin and 1 pins could be output.  Info: Location N9 (pad PAD_70) : Pin out_port_from_the_led_pio[3] of type output uses 2.5 V I/O standard  Info: The following 12 location(s) shared the same VCCIO and ground pair and 10 pin(s) are placed.  Info: Location U3 (pad PAD_68) : Pin mem_dqs_to_and_from_the_ddr_sdram[0] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location V3 (pad PAD_69) : Pin mem_dm_from_the_ddr_sdram[0] of type output uses SSTL-2 Class I I/O standard  Info: Location N9 (pad PAD_70) : Pin out_port_from_the_led_pio[3] of type output uses 2.5 V I/O standard  Info: Location U4 (pad PAD_71) : Pin mem_dq_to_and_from_the_ddr_sdram[0] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location V4 (pad PAD_72) : Pin mem_dq_to_and_from_the_ddr_sdram[1] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location U5 (pad PAD_73) : Pin mem_addr_from_the_ddr_sdram[1] of type output uses SSTL-2 Class I I/O standard  Info: Location V5 (pad PAD_74) : Pin mem_dq_to_and_from_the_ddr_sdram[3] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location (pad PAD_75) : unused  Info: Location R8 (pad PAD_76) : Pin mem_dq_to_and_from_the_ddr_sdram[2] of type bi-directional uses SSTL-2 Class I I/O standard  Info: Location T8 (pad PAD_77) : unused  Info: Location P8 (pad PAD_78) : Pin mem_addr_from_the_ddr_sdram[4] of type output uses SSTL-2 Class I I/O standard  Info: Location P9 (pad PAD_79) : Pin mem_dq_to_and_from_the_ddr_sdram[4] of type bi-directional uses SSTL-2 Class I I/O standard   I am a starter of sopc builder user. I meet this problem when i use the ip core of ddr hp control. I also have saw some similar problems in this forum,and then do as they said,set dm,addr as enable output group ,parrently that does not work.   i use the altera standerd development board ,so i think the placement of all the pin must be no problem.   I think there is something wrong with my setting.i have been with the trouble for some days ,is there anyone can help me?

[Altera_Forum]

Actually the board is the problem. You have to remove the led pin from the design. Just like the error is telling you, there are too many output pins per VREF group. Either a small mistake or a design tradeoff they made when designing the board. 

 Jake

[Altera_Forum]

Typically one of this cases brings up problems like you have reported: 

 - You have a development kit with a basically functional reference design and applied arbitrary changes without understanding exactly, how the design works.  - You let the MegaWizard generate a DDR RAM interface, but skipped some of the suggested steps.  - You tried to assign all location and IO-standards manually without understanding the requirements.  It's not clear from your post, which case applies here.

[Altera_Forum]

I have met the same situation about this.Your warning is nearly as the same as mine.At the beginning, I thought it may be my niosII design.But when I saw a cyclone III example,I found that it is not possible to have a 4 bit wide LED pio,because the LED pins are too close to the SDRAM pins.So I think it may be the sdram and led are confliction in some extent.I change 4 led to one led,then I compile passed!

[Altera_Forum]

thank you for your replying and answering! I solved the problems with almost the same method to you times ago. Although I know little about the hardware design in FPGA project, that problem should be a serious fault terasic made. How can they assume that we would not use both of the parts at the same time! I am really confused!

[Altera_Forum]

--- Quote Start ---  that problem should be a serious fault terasic made. How can they assume that we would not use both of the parts at the same time! I am really confused  --- Quote End ---    There are more concurrent requirements for a dev kit than for a user board. It may be impossible to meet all of them at the same time. However, if you're able to assume the LED output as a static signal that won't disturb RAM operation, you may want to give it a toggle rate 0 mhz assignment, and the fitter will ignore it.