help，nios communicate with fpga

[Altera_Forum]

I want to nios2 communicate with fpga real-time,like cpu and fpga. 

but I can't find the ip core .please show me the ,thank you.

[Altera_Forum]

Typically the niosII uses "avalon" buses to communicate with all of it's peripherals. All you need to do is connect your FPGA to these avalon buses. 

 Both niosII, avalon and FPGA IP are inside a single FPGA. Therefore they can communicate in real-time (the latency should be just a couple of clock cycles)

[Altera_Forum]

thank you , 

I use the avalon bus,but it is not pin to FPGA.  xilinx use the dual RAM,one port connect blaze ,the other connect FPGA.  how about nios2?  for example:  I want to do this   always @(posedge clkin)  begin  case(nios_address)  0:  reg_a <= nios_dat;  1:  reg_b <= nios_dat;  ........  endcase  end

[Altera_Forum]

I used Xilinx a long time ago. In Xilinx World the Micro/picoblaze at that time communicated to the other components using buses: OPB and PLB for example. 

The name for EDK in Altera World is SOPC Builder (or Qsys if you want to try the newest).  Take a look to Avalon Bus Specifications: you may find some details. Someone on this forum also posted some examples of custom components using avalon bus.  Hope this helps you.   I have some difficulties to understand why you want to make the *blaze/Nios II communicate with the FPGA: it is built with FPGA resources. It may be a language problem since English is not my mother tongue.

[Altera_Forum]

thank you. 

English is not my mother tongue,  I want to do "blaze/Nios II communicate with the FPGA",because the cpu and fpga work like this.  thank you for help ,my enlish is poor.Some things can not express clearly.